NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 379

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
Intel
®
ICH8 Family Datasheet
(Desktop
(Mobile
(Mobile
Only)
Only)
Only)
3:2
1:0
Bit
6
5
4
3
2
i64_EN. Software sets this bit to indicate that the processor is an IA_64 processor,
not an IA_32 processor. This may be used in various state machines where there
are behavioral differences.
CPU SLP# Enable (CPUSLP_EN) — R/W.
0 = Disable.
1 = Enables the CPUSLP# signal to go active in the S1 state. This reduces the
NOTE: CPUSLP# will go active during Intel SpeedStep
SMI_LOCK — R/WO. When this bit is set, writes to the GLB_SMI_EN bit (PMBASE
+ 30h, bit 0) will have no effect. Once the SMI_LOCK bit is set, writes of 0 to
SMI_LOCK bit will have no effect (i.e., once set, this bit can only be cleared by
PLTRST#).
Reserved
Intel SpeedStep Enable (SS_EN) — R/W.
0 = Intel SpeedStep technology logic is disabled and the SS_CNT register will not
1 = Intel SpeedStep technology logic is enabled.
PCI CLKRUN# Enable (CLKRUN_EN) — R/W.
0 = Disable. ICH8 drives the CLKRUN# signal low.
1 = Enable CLKRUN# logic to control the system PCI clock via the CLKRUN# and
NOTE: when the SLP_EN# bit is set, the ICH8 drives the CLKRUN# signal low
Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control the
rate at which periodic SMI# is generated.
00 = 64 seconds
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
processor power.
be visible (reads to SS_CNT will return 00h and writes will have no effect).
STP_PCI# signals.
on entry to C3 and C4 states even if this bit is not set.
regardless of the state of the CLKRUN_EN bit. This ensures that the PCI and
LPC clocks continue running during a transition to a sleep state.
Description
®
technology transitions and
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