NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 568

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.4
Note:
14.1.5
568
PCISTS—PCI Status Register
(USB—D29:F0/F1/F2, D26:F0/F1)
Address Offset:
Default Value:
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
RID—Revision Identification Register
(USB—D29:F0/F1/F2, D26:F0/F1)
Offset Address: 08h
Default Value:
10:9
7:0
2:0
Bit
Bit
15
14
13
12
11
8
7
6
5
4
3
Revision ID — RO. Refer to the Intel
Update for the value of the Revision ID Register
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = Set when a data parity error data parity error is detected on writes to the UHCI
Reserved as 0b. Read Only.
Received Master Abort (RMA) — R/WC.
0 = No master abort generated by USB.
1 = USB, as a master, generated a master abort.
Reserved. Always read as 0.
Signaled Target Abort (STA) — R/WC.
0 = ICH8 did Not terminate transaction for USB function with a target abort.
1 = USB function is targeted with a transaction that the ICH8 terminates with a target
DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field defines the timing for
DEVSEL# assertion. These read only bits indicate the ICH8's DEVSEL# timing when
performing a positive decode. ICH8 generates DEVSEL# with medium timing for USB.
Data Parity Error Detected (DPED) — RO. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
User Definable Features (UDF) — RO. Hardwired to 0.
66 MHz Capable — RO. Hardwired to 0.
Capabilities List — RO. Hardwired to 0.
Interrupt Status — RO. This bit reflects the state of this function’s interrupt at the
input of the enable/disable logic.
0 = Interrupt is deasserted.
1 = Interrupt is asserted.
The value reported in this bit is independent of the value in the Interrupt Enable bit.
Reserved
register space or on read completions returned to the host controller.
abort.
See bit description
06h
0280h
–
07h
®
Description
Description
I/O Controller Hub 8 (ICH8) Family Specification
Attribute:
Size:
Attribute:
Size:
RO
8 bits
R/WC, RO
16 bits
UHCI Controllers Registers
Intel
®
ICH8 Family Datasheet