NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 304
NH82801HBM S LB9A
Manufacturer Part Number
NH82801HBM S LB9A
Description
CONTROLLER HUB, ICH8M, I/O, 82801HBM
Manufacturer
Intel
Datasheet
1.NH82801HBM_S_LB9A.pdf
(890 pages)
Specifications of NH82801HBM S LB9A
Power Dissipation Pd
2.4W
Digital Ic Case Style
BGA
No. Of Pins
676
Pci Bus Type
I/O Controller Hub
Pci Express Base Spec
PCIe 1.1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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31:26
23:22
Bit
25
24
21
20
19
18
17
16
15
14
Reserved
Serial ATA Disable 2 (SAD2)— R/W. Default is 0.
0 = The SATA controller #2 (D31:F5) is enabled.
1 = The SATA controller #2 (D31:F5) is disabled.
Thermal Throttle Disable (TTD) — R/W. Default is 0.
0 = Thermal Throttle is enabled.
1 = Thermal Throttle is disabled.
Reserved
PCI Express* 6 Disable (PE6D) — R/W. Default is 0. When disabled, the link for
this port is put into the “link down” state.
0 = PCI Express* port #6 is enabled.
1 = PCI Express port #6 is disabled.
PCI Express 5 Disable (PE5D) — R/W. Default is 0. When disabled, the link for this
port is put into the link down state.
0 = PCI Express port #5 is enabled.
1 = PCI Express port #5 is disabled.
PCI Express 4 Disable (PE4D) — R/W. Default is 0. When disabled, the link for this
port is put into the “link down” state.
0 = PCI Express* port #4 is enabled.
1 = PCI Express port #4 is disabled.
PCI Express 3 Disable (PE3D) — R/W. Default is 0. When disabled, the link for this
port is put into the link down state.
0 = PCI Express port #3 is enabled.
1 = PCI Express port #3 is disabled.
PCI Express 2 Disable (PE2D) — R/W. Default is 0. When disabled, the link for this
port is put into the link down state.
0 = PCI Express port #2 is enabled.
1 = PCI Express port #2 is disabled.
PCI Express 1 Disable (PE1D) — R/W. Default is 0. When disabled, the link for this
port is put into the link down state.
0 = PCI Express port #1 is enabled.
1 = PCI Express port #1 is disabled.
EHCI #1 Disable (EHCI1D) — R/W. Default is 0.
0 = The EHCI #1 is enabled.
1 = The EHCI #1 is disabled.
LPC Bridge Disable (LBD) — R/W. Default is 0.
0 = The LPC bridge is enabled.
1 = The LPC bridge is disabled. Unlike the other disables in this register, the following
Memory cycles in the LPC BIOS range below 4 GB will still be decoded when this bit is
set, but the aliases at the top of 1 MB (the E and F segment) no longer will be
decoded.
• · Memory cycles below 16 MB (1000000h)
• · I/O cycles below 64 KB (10000h)
• · The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF
additional spaces will no longer be decoded by the LPC bridge:
Description
Chipset Configuration Registers
Intel
®
ICH8 Family Datasheet
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