NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 565
NH82801HBM S LB9A
Manufacturer Part Number
NH82801HBM S LB9A
Description
CONTROLLER HUB, ICH8M, I/O, 82801HBM
Manufacturer
Intel
Datasheet
1.NH82801HBM_S_LB9A.pdf
(890 pages)
Specifications of NH82801HBM S LB9A
Power Dissipation Pd
2.4W
Digital Ic Case Style
BGA
No. Of Pins
676
Pci Bus Type
I/O Controller Hub
Pci Express Base Spec
PCIe 1.1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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UHCI Controllers Registers
14
14.1
Note:
Table 129.
Note:
Table 130.
Intel
®
ICH8 Family Datasheet
UHCI Controllers Registers
PCI Configuration Registers
(USB—D29:F0/F1/F2, D26:F0/F1)
The USB functions may be hidden based on the value of the corresponding bits in the
Function Disable Register (see Chipset Configuration Registers). UHCIs must be
disabled from highest number to lowest within their specific PCI device.
UHCI Controller PCI Configuration Map
Register address locations that are not shown in
Reserved (see
UHCI Controller PCI Register Address Map (USB—D29:F0/F1/F2, D26:F0/F1)
(Sheet 1 of 2)
2C–2Dh
00–01h
02–03h
04–05h
06–07h
20–23h
2E–2Fh
Offset
0Ah
0Bh
0Dh
3Ch
08h
09h
0Eh
UHCI #1
UHCI #2
UHCI #3
UHCI #4
UHCI #5
UHCI
Mnemonic
HEADTYP
PCICMD
PCISTS
INT_LN
BASE
Device:Function
SVID
Section 6.2
SCC
BCC
VID
DID
RID
MLT
SID
PI
D29:F0
D29:F1
D29:F2
D26:F0
D26:F1
PCI
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Programming Interface
Sub Class Code
Base Class Code
Master Latency Timer
Header Type
Base Address
Subsystem Vendor Identification
Subsystem Identification
Interrupt Line
for details).
Register Name
Table 130
Notes
and should be treated as
UHCI #1–5
See register
See register
See register
00000001h
description
description
description
Default
8086h
0000h
0280h
0000h
0000h
00h
03h
0Ch
00h
00h
R/WC, RO
R/W, RO
R/W, RO
R/WO
R/WO
Type
R/W
RO
RO
RO
RO
RO
RO
RO
RO
565
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