NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 230

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.20.3
5.20.3.1
5.20.3.2
5.20.4
230
Bus Timing
Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the ICH8
as an SMBus master would like. They have the capability of stretching the low time of
the clock. When the ICH8 attempts to release the clock (allowing the clock to go high),
the clock will remain low for an extended period of time.
The ICH8 monitors the SMBus clock line after it releases the bus to determine whether
to enable the counter for the high time of the clock. While the bus is still low, the high
time counter must not be enabled. Similarly, the low period of the clock can be
stretched by a SMBus master if it is not ready to send or receive data.
Bus Time Out (Intel
If there is an error in the transaction, such that an SMBus device does not signal an
acknowledge, or holds the clock lower than the allowed time-out time, the transaction
will time out. The ICH8 will discard the cycle and set the DEV_ERR bit. The time out
minimum is 25 ms (800 RTC clocks). The time-out counter inside the ICH8 will start
after the last bit of data is transferred by the ICH8 and it is waiting for a response.
The 25 ms timeout counter will not count under the following conditions:
Interrupts / SMI#
The ICH8 SMBus controller uses PIRQB# as its interrupt pin. However, the system can
alternatively be set up to generate SMI# instead of an interrupt, by setting the
SMBUS_SMI_EN bit (Device 31:Function 0:Offset 40h:bit 1).
Table 90
the generation of the interrupt, Host and Slave SMI, and Wake internal signals. The
rows in the tables are additive, which means that if more than one row is true for a
particular scenario then the Results for all of the activated rows will occur.
1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, bit 7) is set
2. The SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is not set (this indicates that
the system has not locked up).
and
Table 91
specify how the various enable bits in the SMBus function control
®
ICH8 as SMBus Master)
Intel
®
Functional Description
ICH8 Family Datasheet