NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 441

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI-to-PCI Bridge Registers (D30:F0)
10.1.19
Intel
®
ICH8 Family Datasheet
BCTRL—Bridge Control Register (PCI-PCI—D30:F0)
Offset Address: 3Eh
Default Value:
15:12
Bit
11
10
9
8
7
6
5
4
Reserved
Discard Timer SERR# Enable (DTE) — R/W. Controls the generation of SERR# on
the primary interface in response to the DTS bit being set:
0 = Do not generate SERR# on a secondary timer discard
1 = Generate SERR# in response to a secondary timer discard
Discard Timer Status (DTS) — R/WC. This bit is set to 1 when the secondary discard
timer (see the SDT bit below) expires for a delayed transaction in the hard state.
Secondary Discard Timer (SDT) — R/W. This bit sets the maximum number of PCI
clock cycles that the Intel® ICH8 waits for an initiator on PCI to repeat a delayed
transaction request. The counter starts once the delayed transaction data is has been
returned by the system and is in a buffer in the ICH8 PCI bridge. If the master has not
repeated the transaction at least once before the counter expires, the ICH8 PCI bridge
discards the transaction from its queue.
0 = The PCI master timeout value is between 2
1 = The PCI master timeout value is between 2
Primary Discard Timer (PDT) — R/W. This bit is R/W for software compatibility only.
Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The PCI logic will not generate
fast back-to-back cycles on the PCI bus.
Secondary Bus Reset (SBR) — R/W. Controls PCIRST# assertion on PCI.
0 = Bridge de-asserts PCIRST#
1 = Bridge asserts PCIRST#. When PCIRST# is asserted, the delayed transaction
Master Abort Mode (MAM) — R/W. Controls the ICH8 PCI bridge’s behavior when a
master abort occurs:
Master Abort on (G)MCH/ICH8 Interconnect (DMI):
0 = Bridge asserts TRDY# on PCI. It drives all 1’s for reads, and discards data on
1 = Bridge returns a target abort on PCI.
Master Abort PCI (non-locked cycles):
0 = Normal completion status will be returned on the (G)MCH/ICH8 interconnect.
1 = Target abort completion status will be returned on the (G)MCH/ICH8 interconnect.
NOTE: All locked reads will return a completer abort completion status on the (G)MCH/
VGA 16-Bit Decode (V16D) — R/W. Enables the ICH8 PCI bridge to provide 16-bits
decoding of VGA I/O address precluding the decode of VGA alias addresses every 1 KB.
This bit requires the VGAE bit in this register be set.
buffers, posting buffers, and the PCI bus are initialized back to reset conditions.
The rest of the part and the configuration registers are not affected.
writes.
ICH8 interconnect.
0000h
–
3Fh
Description
Attribute:
Size:
15
10
and 2
and 2
16
11
PCI clocks
PCI clocks
R/WC, RO
16 bits
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