NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 437

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI-to-PCI Bridge Registers (D30:F0)
10.1.10
10.1.11
Intel
®
ICH8 Family Datasheet
SMLT—Secondary Master Latency Timer Register
(PCI-PCI—D30:F0)
Offset Address: 1Bh
Default Value:
This timer controls the amount of time the ICH8 PCI-to-PCI bridge will burst data on its
secondary interface. The counter starts counting down from the assertion of FRAME#.
If the grant is removed, then the expiration of this counter will result in the de-
assertion of FRAME#. If the grant has not been removed, then the ICH8 PCI-to-PCI
bridge may continue ownership of the bus.
IOBASE_LIMIT—I/O Base and Limit Register
(PCI-PCI—D30:F0)
Offset Address: 1Ch-1Dh
Default Value:
15:12
11:8
7:3
2:0
7:4
3:0
Bit
Bit
Master Latency Timer Count (MLTC) — R/W. This 5-bit field indicates the number of
PCI clocks, in 8-clock increments, that the ICH8 remains as master of the bus.
Reserved
I/O Limit Address Limit bits[15:12] — R/W. I/O Base bits corresponding to address
lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.
II/O Limit Address Capability (IOLC) — RO. Indicates that the bridge does not support
32-bit I/O addressing.
I/O Base Address (IOBA) — R/W. I/O Base bits corresponding to address lines 15:12
for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.
I/O Base Address Capability (IOBC) — RO. Indicates that the bridge does not
support 32-bit I/O addressing.
00h
0000h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W, RO
8 bits
R/W, RO
16 bits
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