NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 335

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
9.1.21
9.1.22
Intel
®
ICH8 Family Datasheet
GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0)
Offset Address: 84h
Default Value:
GEN2_DEC—LPC I/F Generic Decode Range 2Register
(LPC I/F—D31:F0)
Offset Address: 88h
Default Value:
31:24
23:18
31:24
23:18
17:16
17:16
15:2
15:2
Bit
Bit
1
0
1
0
Reserved
Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates
that any value in the corresponding address bit in a received cycle will be treated as a
match. The corresponding bit in the Address field, below, is ignored. The mask is only
provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
Reserved
Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W. This address is
aligned on a 128-byte boundary, and must have address lines 31:16 as 0.
NOTE: The ICH8 Does not provide decode down to the word or byte level
Reserved
Generic Decode Range 1 Enable (GEN1_EN) — R/W.
0 = Disable.
1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F
Reserved
Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates
that any value in the corresponding address bit in a received cycle will be treated as a
match. The corresponding bit in the Address field, below, is ignored. The mask is only
provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
Reserved
Generic I/O Decode Range 2Base Address (GEN1_BASE) — R/W.
NOTE: The ICH8 Does not provide decode down to the word or byte level
Reserved
Generic Decode Range 2Enable (GEN2_EN) — R/W.
0 = Disable.
1 = Enable the GEN2 I/O range to be forwarded to the LPC I/F
00000000h
00000000h
–
–
87h
8Bh
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/W
32 bit
Core
R/W
32 bit
Core
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