NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 380

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.8.1.2
380
GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0)
Offset Address: A2h
Default Value:
Lockable:
(Desktop
(Mobile
Only)
Only)
6:5
6:5
Bit
7
4
3
DRAM Initialization Bit — R/W. This bit does not effect hardware functionality in
any way. BIOS is expected to set this bit prior to starting the DRAM initialization
sequence and to clear this bit after completing the DRAM initialization sequence.
BIOS can detect that a DRAM initialization sequence was interrupted by a reset by
reading this bit during the boot sequence.
Reserved
CPU PLL Lock Time (CPLT) — R/W. This field indicates the amount of time that the
processor needs to lock its PLLs. This is used wherever timing t250–t274 (see
Chapter
00 = min 30.7 µs (Default)
01 = min 61.4 µs
10 = min 122.8 µs
11 = min 245.6 µs
It is the responsibility of the BIOS to program the correct value in this field prior to
the first transition to C3 or C4 states (or performing Intel SpeedStep technology
transitions).
NOTE: The new DPSLP-TO-SLP bits (D31:FO:AAh, bits 1:0) act as an override to
NOTE: These bits are not cleared by any type of reset except RSMRST# or a CF9
System Reset Status (SRS) — R/WC. Software clears this bit by writing a 1 to it.
0 = SYS_RESET# button Not pressed.
1 = ICH8 sets this bit when the SYS_RESET# button is pressed. BIOS is expected to
NOTE: This bit is also reset by RSMRST# and CF9h resets.
CPU Thermal Trip Status (CTS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when PLTRST# is inactive and THRMTRIP# goes active while the
NOTES:
1.
2.
• If the bit is 1, then the DRAM initialization was interrupted.
• This bit is reset by the assertion of the RSMRST# pin.
read this bit and clear it, if it is set.
system is in an S0 or S1 state.
00h
No
these bits.
write
This bit is also reset by RSMRST#, and CF9h resets. It is not reset by the
shutdown and reboot associated with the CPUTHRMTRIP# event.
The CF9h reset in the description refers to CF9h type core well reset which
includes SYS_RST#, PWROK/VRMPWRGD low, SMBus hard reset, TCO
Timeout. This type of reset will clear CTS bit.
23) applies.
Description
Attribute:
Size:
Usage:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/W, R/WC
8-bit
ACPI, Legacy
Resume
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®
ICH8 Family Datasheet