NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 112

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.1.5
Table 39.
Note:
5.1.6
5.1.7
112
Peer Cycles
The PCI bridge may be the initiator of peer cycles. Peer cycles include memory, IO, and
configuration cycle types. Peer cycles are only allowed through VC0, and are enabled
with the following bits:
When enabled for peer for one of the above cycle types, the PCI bridge will perform a
peer decode to see if a peer agent can receive the cycle. When not enabled, memory
cycles (posted and/or non-posted) are sent to DMI, and I/O and/or configuration cycles
are not claimed.
Configuration cycles have special considerations. Under the PCI Local Bus Specification,
these cycles are not allowed to be forwarded upstream through a bridge. However, to
enable things such as manageability, BPC.CDE can be set. When set, type 1 cycles are
allowed into the part. The address format of the type 1 cycle is slightly different from a
standard PCI configuration cycle to allow addressing of extended PCI space. The format
is as follows:
Type 1 Address Format
The ICH8’s IDE (Mobile only) and USB controllers cannot perform peer-to-peer traffic.
PCI-to-PCI Bridge Model
From a software perspective, the ICH8 contains a PCI-to-PCI bridge. This bridge
connects DMI to the PCI bus. By using the PCI-to-PCI bridge software model, the ICH8
can have its decode ranges programmed by existing plug-and-play software such that
PCI ranges do not conflict with graphics aperture ranges in the Host controller.
IDSEL to Device Number Mapping
When addressing devices on the external PCI bus (with the PCI slots), the ICH8 asserts
one address signal as an IDSEL. When accessing device 0, the ICH8 asserts AD16.
When accessing Device 1, the ICH8 asserts AD17. This mapping continues all the way
up to device 15 where the ICH8 asserts AD31. Note that the ICH8’s internal functions
(Intel High Definition Audio, IDE (Mobile only), USB, SATA and PCI Bridge) are
enumerated like they are off of a separate PCI bus (DMI) from the external PCI bus.
31:27
26:24
23:16
15:11
10:8
7:2
1
0
• BPC.PDE (D30:F0:Offset 4Ch:bit 2) – Memory and I/O cycles
• BPC.CDE (D30:F0:Offset 4Ch:bit 1) – Configuration cycles
Bits
Reserved (same as the PCI Local Bus Specification)
Extended Configuration Address – allows addressing of up to 4K. These bits are
combined with bits 7:2 to get the full register.
Bus Number (same as the PCI Local Bus Specification)
Device Number (same as the PCI Local Bus Specification)
Function Number (same as the PCI Local Bus Specification)
Register (same as the PCI Local Bus Specification)
0
Must be 1 to indicate a type 1 cycle. Type 0 cycles are not decoded.
Definition
Intel
®
Functional Description
ICH8 Family Datasheet