NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 480

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.1.25
Note:
480
IDE_CONFIG—IDE I/O Configuration Register
(SATA–D31:F2)
Address Offset: 54h
Default Value:
This register is R/W to maintain software compatibility and enable parallel ATA
functionality when the PCI functions are combined. These bits have no effect on SATA
operation, unless otherwise noted.
31:24
23:20
19:18
17:16
Bit
15
14
Reserved
Scratchpad (SP2). Intel
SEC_SIG_MODE — R/W. These bits are used to control mode of the Secondary IDE
signal pins for swap bay support.
If the SRS bit (Chipset Configuration Registers:Offset 3414h:bit 1) is 1, the reset states
of bits 19:18 will be 01 (tri-state) instead of 00 (normal).
00 = Normal (Enabled)
01 = Tri-state (Disabled)
10 = Drive low (Disabled)
11 = Reserved
NOTE: In the non-combined mode, these bits are for software compatibility and have
PRIM_SIG_MODE — R/W. These bits are used to control mode of the Primary IDE
signal pins for mobile swap bay support.
If the PRS bit (Chipset Confide Registers:Offset 3414h:bit 1) is 1, the reset states of
bits 17:16 will be 01 (tri-state) instead of 00 (normal).
00 = Normal (Enabled)
01 = Tri-state (Disabled)
10 = Drive low (Disabled)
11 = Reserved
NOTE: In the non-combined mode, these bits are for software compatibility and have
Fast Secondary Drive 1 Base Clock (FAST_SCB1) — R/W. This bit is used in
conjunction with the SCT1 bits (D31:F2:4Ah, bits 13:12) to enable/disable Ultra ATA/
100 timings for the Secondary Slave drive.
0 = Disable Ultra ATA/100 timing for the Secondary Slave drive.
1 = Enable Ultra ATA/100 timing for the Secondary Slave drive (overrides bit 3 in this
Fast Secondary Drive 0 Base Clock (FAST_SCB0) — R/W. This bit is used in
conjunction with the SCT0 bits (D31:F2:4Ah, bits 9:8) to enable/disable Ultra ATA/100
timings for the Secondary Master drive.
0 = Disable Ultra ATA/100 timing for the Secondary Master drive.
1 = Enable Ultra ATA/100 timing for the Secondary Master drive (overrides bit 2 in this
register).
register).
no effect on the SATA controller. In the combined mode, these bits are
controlling the behavior of the PATA controller. (Mobile Only)
no effect on the SATA controller. In the combined mode, these bits are
controlling the behavior of the PATA controller. (Mobile Only)
00000000h
–
57h
®
ICH8 does not perform any actions on these bits.
Description
Attribute:
Size:
SATA Controller Registers (D31:F2)
R/W
32 bits
Intel
®
ICH8 Family Datasheet