NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 183

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.13.12.1
5.13.13
5.13.13.1
5.13.13.2
Intel
®
ICH8 Family Datasheet
Clock Control Signals from Intel
Synthesizer (Mobile Only)
The clock generator is assumed to have direct connect from the following ICH8 signals:
Legacy Power Management Theory of Operation
Instead of relying on ACPI software, legacy power management uses BIOS and various
hardware mechanisms. The scheme relies on the concept of detecting when individual
subsystems are idle, detecting when the whole system is idle, and detecting when
accesses are attempted to idle subsystems.
However, the operating system is assumed to be at least APM enabled. Without APM
calls, there is no quick way to know when the system is idle between keystrokes. The
ICH8 does not support burst modes.
APM Power Management (Desktop Only)
The ICH8 has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and
Enable register, generates an SMI# once per minute. The SMI handler can check for
system activity by reading the DEVACT_STS register. If none of the system bits are set,
the SMI handler can increment a software counter. When the counter reaches a
sufficient number of consecutive minutes with no activity, the SMI handler can then put
the system into a lower power state.
If there is activity, various bits in the DEVACT_STS register will be set. Software clears
the bits by writing a 1 to the bit position.
The DEVACT_STS register allows for monitoring various internal devices, or Super I/O
devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions
on LPC or PCI. Other PCI activity can be monitored by checking the PCI interrupts.
Mobile APM Power Management (Mobile Only)
In mobile systems, there are additional requirements associated with device power
management. To handle this, the ICH8 has specific SMI# traps available. The following
algorithm is used:
The SMI# handler exits with an I/O restart. This allows the original software to
continue.
1. The periodic SMI# timer checks if a device is idle for the require time. If so, it puts
2. When software (not the SMI# handler) attempts to access the device, a trap occurs
3. The SMI# handler turns on the device and turns off the trap
• STP_CPU#: Stops processor clocks in C3 and C4 states
• STP_PCI#: Stops system PCI clocks (not the ICH8 free-running 33 MHz clock) due
• SLP_S3#: Expected to drive clock chip PWRDOWN (through inverter), to stop
to CLKRUN# protocol
clocks in S3 to S5.
the device into a low-power state and sets the associated SMI# trap.
(the cycle does not really go to the device and an SMI# is generated).
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ICH8 to Clock
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