NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 794

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.1.15
21.1.16
21.1.17
21.1.18
794
SVID—Subsystem Vendor ID
Address Offset: 2Ch
Default Value:
This register should be implemented for any function that could be instantiated more
than once in a given system,. The SVID register, in combination with the Subsystem ID
register, enables the operating environment to distinguish one subsystem from the
other(s).
Software (BIOS) will write the value to this register. After that, the value can be read,
but writes to the register will have no effect. The write to this register should be
combined with the write to the SID to create one 32-bit write. This register is not
affected by D3
SID—Subsystem ID
Address Offset: 2Eh
Default Value:
This register should be implemented for any function that could be instantiated more
than once in a given system,. The SID register, in combination with the Subsystem
Vendor ID register, make it possible for the operating environment to distinguish one
subsystem from the other(s).
Software (BIOS) will write the value to this register. Then, the value can be read, but
writes to the register will have no effect. The write to this register should be combined
with the write to the SVID to create one 32-bit write. This register is not affected by
D3
CAP_PTR —Capabilities Pointer
Address Offset: 34h
Default Value:
INTLN—Interrupt Line
Address Offset: 3Ch
Default Value:
15:0
15:0
Bit
Bit
7:0
7:0
Bit
Bit
HOT
to D0 reset.
SVID (SVID) — R/WO. These R/WO bits have no ICH8 functionality.
SID (SID) — R/WO. These R/WO bits have no ICH8 functionality.
Capability Pointer (CP) — RO. This field indicates that the first capability pointer
offset is offset 50h (Power Management Capability).
Interrupt Line — R/W. The ICH8 hardware does not use this field directly. It is used
to communicate to software the interrupt line that the interrupt pin is connected to.
HOT
0000h
0000h
50h
00h
to D0 reset.
–
–
2Fh
2Dh
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Thermal Sensor Registers (D31:F6)
R/WO
16 bits
R/WO
16 bits
RO
8 bits
R/W
8 bits
Intel
®
ICH8 Family Datasheet