NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 252

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.28
5.28.1
252
Serial POST Codes Over GPIO
ICH8 adds the extended capability allowing system software to serialize POST or other
messages on GPIO. This capability negates the requirement for dedicated diagnostic
LEDs on the platform. Additionally, based on the newer BTX form factors, the PCI bus
as a target for POST codes is increasingly difficult to support as the total number of PCI
devices supported are decreasing.
Theory of operation
For the ICH8, generation POST code serialization logic will be shared with GPIO. These
GPIO will likely be shared with LED control offered by the Super I/O (SIO) component.
The anticipated usage model is that either the ICH8 or the SIO can drive a pin low to
turn off an LED. In the case of the power LED, the SIO would normally leave its
corresponding pin in a high-Z state to allow the LED to turn on. In this state, the ICH8
can blink the LED by driving its corresponding pin low and subsequently tri-stating the
buffer.
An external optical sensing device can detect the on/off state of the LED. By externally
post-processing the information from the optical device, the serial bit stream can be
recovered. The hardware will supply a ‘sync’ byte before the actual data transmission
to allow external detection of the transmit frequency. The frequency of transmission
should be limited to 1 transition every 1usec to ensure the detector can reliably sample
the on/off state of the LED. To allow flexibility in pull-up resistor values for power
optimization, the frequency of the transmission is programmable via the DRS field in
the GP_SB_CMDSTS register (See
The serial bit stream is Manchester encoded. This choice of transmission ensures that a
transition will be seen on every clock. The 1 or 0 data is based on the transmission
happening during the high or low phase of the clock.
A simplified hardware/software register interface provides control and status
information to track the activity of this block. Software enabling the serial blink
capability should implement an algorithm referenced below to send the serialized
message on the enabled GPIO.
By providing a generic capability that can be used both in the main and the suspend
power planes, maximum flexibility can be achieved. A key point to make is that the
ICH8 will not unintentionally drive the LED control pin low unless a serialization is in
progress. System board connections using this serialization capability are required to
use the same power plane controlling the LED as the ICH8 GPIO pin. Otherwise, the
ICH8 GPIO may float low during the message and prevent the LED from being
controlled from the SIO. The hardware will only be serializing messages when the core
power well is powered and the processor is operational.
Care should be taken to prevent the ICH8 from driving an active ‘1’ on a pin sharing the
serial LED capability. Since the SIO could be driving the line to 0, having the ICH8 drive
a 1 would create a high current path. A recommendation to avoid this condition
involves choosing a GPIO defaulting to an input. The GP_SER_BLINK register (See
1. Read the Go/Busy status bit in the GP_SB_CMDSTS register and verify it is cleared.
2. Write the data to serialize into the GP_SB_DATA register.
3. Write the DLS and DRS values into the GP_SB_CMDSTS register and set the Go bit.
This will ensure that the GPIO is idled and a previously requested message is still
not in progress.
This may be accomplished using a single write.
Section
9.10.7).
Intel
®
Functional Description
ICH8 Family Datasheet