NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 710

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.1.23
18.1.24
710
CLIST—Capabilities List Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 40–41h
Default Value:
XCAP—PCI Express* Capabilities Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 42h–43h
Default Value:
15:14
15:8
13:9
7:0
7:4
3:0
Bit
Bit
Bit
3
2
1
0
8
VGA Enable (VE)— R/W.
0 = Disable. The ranges below will not be claimed off the backbone by the root port.
1 = Enable. The following ranges will be claimed off the backbone by the root port:
ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the
I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space.
0 = Disable. The root port will not block any forwarding from the backbone as described
1 = Enable. The root port will block any forwarding from the backbone to the device of
SERR# Enable (SE) — R/W.
0 = Disable. The messages described below are not forwarded to the backbone.
1 = Enable. ERR_COR, ERR_NONFATAL, and ERR_FATAL messages received are
Parity Error Response Enable (PERE) — R/W. When set,
0 = Disable. Poisoned write TLPs and completions indicating poisoned TLPs will not set
1 = Enable. Poisoned write TLPs and completions indicating poisoned TLPs will set the
Next Capability (NEXT) — RO. Value of 80h indicates the location of the next pointer.
Capability ID (CID) — RO. Indicates this is a PCI Express* capability.
Reserved
Interrupt Message Number (IMN) — RO. The Intel
MSI interrupt numbers.
Slot Implemented (SI) — R/WO. This bit indicates whether the root port is connected
to a slot. Slot support is platform specific. BIOS programs this field, and it is maintained
until a platform reset.
Device / Port Type (DT) — RO. Indicates this is a PCI Express* root port.
Capability Version (CV) — RO. Indicates PCI Express 1.0.
• Memory ranges A0000h–BFFFFh
• I/O ranges 3B0h – 3BBh and 3C0h – 3DFh, and all aliases of bits 15:10 in any combination of 1s
below.
I/O transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to
3FFh).
forwarded to the backbone.
the SSTS.DPD (D28:F0/F1/F2/F3/F4/F5:1E, bit 8).
SSTS.DPD (D28:F0/F1/F2/F3/F4/F5:1E, bit 8).
8010h
0041h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
PCI Express* Configuration Registers
®
ICH8 does not have multiple
RO
16 bits
R/WO, RO
16 bits
Intel
®
ICH8 Family Datasheet