NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 749

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface (SPI)
20.1.2
Intel
®
ICH8 Family Datasheet
HSFS—Hardware Sequencing Flash Status Register
(
Memory Address:SPIBAR + 04h
Default Value:
SPI Memory Mapped Configuration Registers
12:6
4:3
Bit
15
14
13
5
2
1
Flash Configuration Lock-Down (FLOCKDN)— R/W/L. When set to 1, the Flash
Program Registers that are locked down by this FLOCKDN bit cannot be written. Once
set to 1, this bit can only be cleared by a hardware reset.
Hardware reset is initiated by one of the following resets:
Flash Descriptor Valid (FDV)— RO. This bit is set to a 1 if the Flash Controller read
the correct Flash Descriptor Signature.
If the Flash Descriptor Valid bit is not 1, software cannot use the Hardware Sequencing
registers, but must use the software sequencing registers. Any attempt to use the
Hardware Sequencing registers will result in the FCERR bit being set.
Flash Descriptor Override Pin-Strap Status (FDOPSS) — RO: This bit reflects the
value the Flash Descriptor Override Pin-Strap.
0 = The Flash Descriptor Override strap is set
1 = No override
Reserved
SPI Cycle In Progress (SCIP)— RO. Hardware sets this bit when software sets the
Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit
remains set until the cycle completes on the SPI interface. Hardware automatically sets
and clears this bit so that software can determine when read data is valid and/or when
it is safe to begin programming the next command. Software must only program the
next command when this bit is 0.
Block/Sector Erase Size (BERASE) — RO. This field identifies the erasable sector
size for all Flash components.
Valid Bit Settings:
00 = 256 Byte
01 = 4 KB
10 = Reserved for future use
11 = 64 KB
made to access the BIOS region using the direct access method or an access to the
BIOS Program Registers that violated the security restrictions. This bit is simply a log of
an access security violation. This bit is cleared by software writing a 1.
Flash Cycle Error (FCERR) — R/W/C. Hardware sets this bit to 1 when an program
register access is blocked to the FLASH due to one of the protection policies or when
any of the programmed cycle registers is written while a programmed access is already
in progress. This bit remains asserted until cleared by software writing a 1 or until
hardware reset occurs. Software must clear this bit before setting the FLASH Cycle GO
bit in this register.
Hardware reset is initiated by one of the following resets:
Access Error Log (AEL)— R/W/C. Hardware sets this bit to a 1 when an attempt was
• Global reset (when the Host and the ME partitions are both reset) - on both ME-enabled and
• Host Partition reset (any time PLTRST# is asserted either from a cold or a warm reset) - only on
• Global reset (when the Host and the ME partitions are both reset) - on both ME-enabled and
• Host Partition reset (any time PLTRST# is asserted either from a cold or a warm reset) - only on
non-ME systems.
ME enabled systems.
non-ME systems.
ME enabled systems.
0000h
Description
Attribute:
Size:
)
RO, R/WC, R/WL
16 bits
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