NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 253

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.28.2
Intel
®
ICH8 Family Datasheet
Section
This sequence ensures the open-drain capability of the buffer is properly configured
before enabling the pin as an output.
Serial Message Format
To serialize the data onto the GPIO, an initial state of hi-Z is assumed. The SIO is
required to have its LED control pin in a high-Z state as well to allow ICH8 to blink the
LED.
The three components of the serial message include the sync, data, and idle fields. The
sync field is 7 bits of ‘1’ data followed by 1 bit of ‘0’ data. Starting from the hi-Z state
(LED on) provides external hardware a known initial condition and a known pattern. In
case one or more of the leading 1 sync bits are lost, the 1’s followed by 0 provide a
clear indication of ‘end of sync’. This pattern will be used to ‘lock’ external sampling
logic to the encoded clock.
The data field is shifted out with the highest byte first (MSB). Within each byte, the
most significant bit is shifted first (MSb).
The idle field is enforced by the hardware and is at least 2 bit times long. The hardware
will not clear the Busy and Go bits until this idle time is met. Supporting the idle time in
hardware prevents time-based counting in BIOS as the hardware is immediately ready
for the next serial code when the Go bit is cleared. Note that the idle state is
represented as a high-Z condition on the pin. If the last transmitted bit is a ‘1’,
returning to the idle state will result in a final 0-1 transition on the output Manchester
data. Two full bit times of idle correspond to a count of 4 time intervals (the width of
the time interval is controlled by the DRS field).
The waveform below shows a 1-byte serial write with a data byte of 5Ah. The internal
clock and bit position are for reference purposes only. The Manchester D is the
resultant data generated and serialized onto the GPIO. Since the buffer is operating in
open-drain mode the transitions are from hi-Z to 0 and back.
Bit
Internal Clock
Manchester D
9.10.7) should be set first before changing the direction of the pin to an output.
7
6
8-bit sync field
5
(1111_1110)
4
3
2
1
§ §
0
5A data byte
2 clk
idle
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