NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 613

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EHCI Controller Registers (D29:F7, D26:F7)
15.2.2.4
Note:
Intel
®
ICH8 Family Datasheet
FRINDEX—Frame Index Register
Offset:
Default Value:
The SOF frame number value for the bus SOF token is derived or alternatively managed
from this register. Refer to Section 4 of the EHCI specification for a detailed explanation
of the SOF value management requirements on the host controller. The value of
FRINDEX must be within 125 µs (1 micro-frame) ahead of the SOF token value. The
SOF value may be implemented as an 11-bit shadow register. For this discussion, this
shadow register is 11 bits and is named SOFV. SOFV updates every 8 micro-frames. (1
millisecond). An example implementation to achieve this behavior is to increment SOFV
each time the FRINDEX[2:0] increments from 0 to 1.
Software must use the value of FRINDEX to derive the current micro-frame number,
both for high-speed isochronous scheduling purposes and to provide the get micro-
frame number function required to client drivers. Therefore, the value of FRINDEX and
the value of SOFV must be kept consistent if chip is reset or software writes to
FRINDEX. Writes to FRINDEX must also write-through FRINDEX[13:3] to
SOFV[10:0]. In order to keep the update as simple as possible, software should never
write a FRINDEX value where the three least significant bits are 111b or 000b.
This register is used by the host controller to index into the periodic frame list. The
register updates every 125 microseconds (once each micro-frame). Bits [12:3] are
used to select a particular entry in the Periodic Frame List during periodic schedule
execution. The number of bits used for the index is fixed at 10 for the ICH8 since it only
supports 1024-entry frame lists. This register must be written as a dword. Word and
byte writes produce undefined results. This register cannot be written unless the Host
controller is in the Halted state as indicated by the HCHalted bit (D29:F7,
D26:F7:CAPLENGTH + 24h, bit 12). A write to this register while the Run/Stop bit
(D29:F7, D26:F7:CAPLENGTH + 20h, bit 0) is set to a 1 (USB2.0_CMD register)
produces undefined results. Writes to this register also effect the SOF value. See
Section 4 of the EHCI specification for details.
31:14
13:0
Bit
Reserved
Frame List Current Index/Frame Number — R/W. The value in this register
increments at the end of each time frame (e.g., micro-frame).
Bits [12:3] are used for the Frame List current index. This means that each location of
the frame list is accessed 8 times (frames or micro-frames) before moving to the next
index.
MEM_BASE + 2Ch–2Fh
00000000h
Description
Attribute:
Size:
R/W
32 bits
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