NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 418

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

418
6:4
Bit
8
7
3
2
1
0
BIOSWR_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = ICH8 sets this bit and generates and SMI# to indicate an invalid attempt to write to
NOTE: On write cycles attempted to the 4 MB lower alias to the BIOS space, the
NEWCENTURY_STS — R/WC. This bit is in the RTC well.
0 = Cleared by writing a 1 to the bit position or by RTCRST# going active.
1 = This bit is set when the Year byte (RTC I/O space, index offset 09h) rolls over from
NOTE: The NEWCENTURY_STS bit is not valid when the RTC battery is first installed (or
Reserved
TIMEOUT — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by ICH8 to indicate that the SMI was caused by the TCO timer reaching 0.
TCO_INT_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = SMI handler caused the interrupt by writing to the TCO_DAT_OUT register
SW_TCO_SMI — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Software caused an SMI# by writing to the TCO_DAT_IN register (TCOBASE +
NMI2SMI_STS — RO.
0 = Cleared by clearing the associated NMI status bit.
1 = Set by the ICH8 when an SMI# occurs because an event occurred that would
The NEWCENTURY_STS bit may take up to 3 RTC clocks for the bit to be cleared
after a 1 is written to the bit to clear it. After writing a 1 to this bit, software should
not exit the SMI handler until verifying that the bit has actually been cleared. This
will ensure that the SMI is not re-entered.
the BIOS. This occurs when either:
a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or
b) any write is attempted to the BIOS and the BIOSWP bit is also set.
99 to 00. Setting this bit will cause an SMI# (but not a wake event).
(TCOBASE + 03h).
02h).
otherwise have caused an NMI (because NMI2SMI_EN is set).
BIOSWR_STS will not be set.
when RTC power has not been maintained). Software can determine if RTC
power has not been maintained by checking the RTC_PWR_STS bit
(D31:F0:A4h, bit 2), or by other means (such as a checksum on RTC RAM). If
RTC power is determined to have not been maintained, BIOS should set the
time to a valid value and then clear the NEWCENTURY_STS bit.
Description
LPC Interface Bridge Registers (D31:F0)
Intel
®
ICH8 Family Datasheet