NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 65

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Description
Table 10.
Intel
®
ICH8 Family Datasheet
PCI Interface Signals (Sheet 3 of 3)
GNT1#/ GPIO51
GNT2#/ GPIO53
GNT3#/GPIO55
PCIRST#
PLOCK#
PCICLK
SERR#
GNT0#
Name
PME#
Type
I/OD
I/OD
I/O
O
O
I
PCI Grants: The ICH8 supports up to 4 masters on the PCI bus.
GNT[3:1]# pins can instead be used as GPIO.
Pull-up resistors are not required on these signals. If pull-ups are
used, they should be tied to the Vcc3_3 power rail.
NOTE: GNT[3:0]# are sampled as a functional strap. See
PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all
transactions on the PCI Bus.
NOTE: (Mobile Only) This clock does not stop based on STP_PCI#
PCI Reset: This is the Secondary PCI Bus reset signal. It is a
logical OR of the primary interface PLTRST# signal and the state of
the Secondary Bus Reset bit of the Bridge Control register
(D30:F0:3Eh, bit 6).
PCI Lock: This signal indicates an exclusive bus operation and may
require multiple transactions to complete. ICH8 asserts PLOCK#
when it performs non-exclusive transactions on the PCI bus.
PLOCK# is ignored when PCI masters are granted the bus in
desktop configurations.
NOTE: In mobile configuration, devices on the PCI bus (other than
System Error: SERR# can be pulsed active by any PCI device that
detects a system error condition. Upon sampling SERR# active, the
ICH8 has the ability to generate an NMI, SMI#, or interrupt.
PCI Power Management Event: PCI peripherals drive PME# to
wake the system from low-power states S1–S5. PME# assertion can
also be enabled to generate an SCI from the S0 state. In some
cases the ICH8 may drive PME# active due to an internal wake
event. The ICH8 will not drive PME# high, but it will be pulled up to
VccSus3_3 by an internal pull-up resistor.
Section 2.26
signal. PCI Clock only stops based on SLP_S3#.
the ICH8) are not permitted to assert the PLOCK# signal.
for details.
Description
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