NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 741

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Precision Event Timer Registers
19
19.1
Table 142.
Intel
®
ICH8 Family Datasheet
High Precision Event Timer
Registers
The timer registers are memory-mapped in a non-indexed scheme. This allows the
processor to directly access each register without having to use an index register. The
timer register space is 1024 bytes. The registers are generally aligned on 64-bit
boundaries to simplify implementation with IA64 processors. There are four possible
memory address ranges beginning at 1) FED0_0000h, 2) FED0_1000h,
3) FED0_2000h., 4) FED0_4000h. The choice of address range will be selected by
configuration bits in the High Precision Timer Configuration Register (Chipset
Configuration Registers:Offset 3404h).
Behavioral Rules:
Memory-Mapped Registers
Memory-Mapped Registers (Sheet 1 of 2)
1. Software must not attempt to read or write across register boundaries. For
2. Software should not write to read only registers.
3. Software should not expect any particular or consistent value when reading
000–007h
010–017h
020–027h
100–107h
120–127h
008–00Fh
018–01Fh
028–0EFh
0F0–0F7h
108–10Fh
110–11Fh
128–12Fh
130–13Fh
0F8–0FFh
Offset
example, a 32-bit access should be to offset x0h, x4h, x8h, or xCh. 32-bit accesses
should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh, 0Dh, 0Eh, or 0Fh.
Any accesses to these offsets will result in an unexpected behavior, and may result
in a master abort. However, these accesses should not result in system hangs.
64-bit accesses can only be to x0h and must not cross 64-bit boundaries.
reserved registers or bits.
TIM0_COMP
TIM1_COMP
TIM0_CONF
TIM1_CONF
Mnemonic
GINTR_STA
GEN_CONF
MAIN_CNT
GCAP_ID
—
—
—
—
—
—
General Configuration
General Capabilities and Identification
Reserved
Reserved
General Interrupt Status
Reserved
Main Counter Value
Reserved
Timer 0 Configuration and Capabilities
Timer 0 Comparator Value
Reserved
Timer 1 Configuration and Capabilities
Timer 1 Comparator Value
Reserved
Register
0429B17F8
086A201h
—
0000h
—
00000000
00000000h
—
N/A
—
N/A
N/A
—
N/A
N/A
—
Default
RO
—
—
R/WC,
R/W
—
—
—
—
R/W
R/W
R/W, RO
R/W
R/W, RO
R/W
Type
741