NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 76

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17.
76
Processor Interface Signals (Sheet 2 of 2)
(Desktop Only)
(Mobile Only) /
CPUPWRGD /
TP2 (Desktop
INIT3_3V#
STPCLK#
A20GATE
IGNNE#
DPSLP#
GPIO49
RCIN#
INIT#
Name
SMI#
INTR
Only)
NMI
Type
O
O
O
O
O
O
O
O
O
I
I
Ignore Numeric Error: This signal is connected to the ignore error
pin on the processor. IGNNE# is only used if the ICH8 coprocessor
error reporting function is enabled in the OIC.CEN register (Chipset
Configuration Registers:Offset 31FFh: bit 1). If FERR# is active,
indicating a coprocessor error, a write to the Coprocessor Error
register (I/O register F0h) causes the IGNNE# to be asserted.
IGNNE# remains asserted until FERR# is negated. If FERR# is not
asserted when the Coprocessor Error register is written, the IGNNE#
signal is not asserted.
Initialization: INIT# is asserted by the ICH8 for 16 PCI clocks to
reset the processor. ICH8 can be configured to support processor Built
In Self Test (BIST).
Initialization 3.3 V: This is the identical 3.3 V copy of INIT#
intended for Firmware Hub.
CPU Interrupt: INTR is asserted by the ICH8 to signal the processor
that an interrupt request is pending and needs to be serviced. It is an
asynchronous output and normally driven low.
Non-Maskable Interrupt: NMI is used to force a non-Maskable
interrupt to the processor. The ICH8 can generate an NMI when either
SERR# is asserted or IOCHK# goes active via the SERIRQ# stream.
The processor detects an NMI when it detects a rising edge on NMI.
NMI is reset by setting the corresponding NMI source enable/disable
bit in the NMI Status and Control register (I/O Register 61h).
System Management Interrupt: SMI# is an active low output
synchronous to PCICLK. It is asserted by the ICH8 in response to one
of many enabled hardware or software events.
Stop Clock Request: STPCLK# is an active low output synchronous
to PCICLK. It is asserted by the ICH8 in response to one of many
hardware or software events. When the processor samples STPCLK#
asserted, it responds by stopping its internal clock.
Keyboard Controller Reset CPU: The keyboard controller can
generate INIT# to the processor. This saves the external OR gate with
the ICH8’s other sources of INIT#. When the ICH8 detects the
assertion of this signal, INIT# is generated for
16 PCI clocks.
NOTE: The ICH8 will ignore RCIN# assertion during transitions to the
A20 Gate: A20GATE is from the keyboard controller. The signal acts
as an alternative method to force the A20M# signal active. It saves
the external OR gate needed with various other chipsets.
CPU Power Good: This signal should be connected to the processor’s
PWRGOOD input to indicate when the processor power is valid. This is
an output signal that represents a logical AND of the ICH8’s PWROK
and VRMPWRGD signals.
This signal may optionally be configured as a GPIO.
Deeper Sleep: DPSLP# is asserted by the ICH8 to the processor.
When the signal is low, the processor enters the deep sleep state by
gating off the processor Core Clock inside the processor. When the
signal is high (default), the processor is not in the deep sleep state.
S1, S3, S4, and S5 states.
Description
Intel
®
ICH8 Family Datasheet
Signal Description