NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 598

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.1.27
Note:
598
LEG_EXT_CS—USB EHCI Legacy Support Extended
Control / Status Register (USB EHCI—D29:F7, D26:F7)
Address Offset:
Default Value:
Power Well:
These bits are not reset by a D3-to-D0 warm rest or a core well reset.
28:22
Bit
31
30
29
21
20
19
18
17
16
SMI on BAR — R/WC. Software clears this bit by writing a 1 to it.
0 = Base Address Register (BAR) not written.
1 = This bit is set to 1 when the Base Address Register (BAR) is written.
SMI on PCI Command — R/WC. Software clears this bit by writing a 1 to it.
0 = PCI Command (PCICMD) Register Not written.
1 = This bit is set to 1 when the PCI Command (PCICMD) Register is written.
SMI on OS Ownership Change — R/WC. Software clears this bit by writing a 1 to it.
0 = No HC OS Owned Semaphore bit change.
1 = This bit is set to 1 when the HC OS Owned Semaphore bit in the LEG_EXT_CAP
Reserved — RO. Hardwired to 00h
SMI on Async Advance — RO. This bit is a shadow bit of the Interrupt on Async
Advance bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the Interrupt on Async
SMI on Host System Error — RO. This bit is a shadow bit of Host System Error bit in
the USB2.0_STS register (D29:F7, D26:F7:CAPLENGTH + 24h, bit 4).
NOTE: To clear this bit system software must write a 1 to the Host System Error bit in
SMI on Frame List Rollover — RO. This bit is a shadow bit of Frame List Rollover bit
(D29:F7, D26:F7:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the Frame List Rollover bit in
SMI on Port Change Detect — RO. This bit is a shadow bit of Port Change Detect bit
(D29:F7, D26:F7:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the Port Change Detect bit in
SMI on USB Error — RO. This bit is a shadow bit of USB Error Interrupt (USBERRINT)
bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 1) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the USB Error Interrupt bit in
SMI on USB Complete — RO. This bit is a shadow bit of USB Interrupt (USBINT) bit
(D29:F7, D26:F7:CAPLENGTH + 24h, bit 0) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the USB Interrupt bit in the
register (D29:F7, D26:F7:68h, bit 24) transitions from 1 to 0 or 0 to 1.
Advance bit in the USB2.0_STS register.
the USB2.0_STS register.
the USB2.0_STS register.
the USB2.0_STS register.
the USB2.0_STS register.
USB2.0_STS register.
Suspend
00000000h
6C
–
6Fh
Description
Attribute:
Size:
EHCI Controller Registers (D29:F7, D26:F7)
R/W, R/WC, RO
32 bits
Intel
®
ICH8 Family Datasheet