NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 365

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
9.5.3
9.5.4
Note:
Note:
Intel
®
ICH8 Family Datasheet
DAT—Data Register (LPC I/F—D31:F0)
Memory Address FEC0_0010h
Default Value:
This is a 32-bit register specifying the data to be read or written to the register pointed
to by the Index register. This register can only be accessed in dword quantities.
EOIR—EOI Register (LPC I/F—D31:F0)
Memory Address FEC0h_0040h
Default Value:
The EOI register is present to provide a mechanism to maintain the level triggered
semantics for level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/O APIC will check the lower 8 bits written
to this register, and compare it with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit (Index Offset 10h,
bit 14) for that I/O Redirection Entry will be cleared.
If multiple I/O Redirection entries, for any reason, assign the same vector for more
than one interrupt input, each of those entries will have the Remote_IRR bit reset to 0.
The interrupt which was prematurely reset will not be lost because if its input remained
active when the Remote_IRR bit is cleared, the interrupt will be reissued and serviced
at a later time. Note: Only bits 7:0 are actually used. Bits 31:8 are ignored by the
ICH8.
To provide for future expansion, the processor should always write a value of 0 to
bits 31:8.
31:8
7:0
7:0
Bit
Bit
APIC Data — R/W. This is a 32-bit register for the data to be read or written to the
APIC indirect register
FEC0_0000h).
Reserved. To provide for future expansion, the processor should always write a value of
0 to Bits 31:8.
Redirection Entry Clear — WO. When a write is issued to this register, the I/O APIC
will check this field, and compare it with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection
Entry will be cleared.
00000000h
N/A
(Figure
109) pointed to by the Index register (Memory Address
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
32 bits
WO
32 bits
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