NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 299

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chipset Configuration Registers
7.1.66
7.1.67
Intel
®
ICH8 Family Datasheet
OIC—Other Interrupt Control Register
Offset Address: 31FF–31FFh
Default Value:
RC—RTC Configuration Register
Offset Address: 3400–3403h
Default Value:
31:5
7:4
3:2
1:0
Bit
Bit
1
0
4
3
2
APIC Range Select (ASEL): These bits define address bits 15:12 for the IOxAPIC
range. The default value of 0h enables compatibility with prior ICH8 products as an
initial value. This value must not be changed unless the IOxAPIC Enable bit is
cleared.
Reserved
Coprocessor Error Enable (CEN) — R/W.
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = If FERR# is low, the Intel
APIC Enable (AEN) — R/W.
0 = The internal IOxAPIC is disabled.
1 = Enables the internal IOxAPIC and its address decode.
NOTE: Software should read this register after modifying APIC Enable bit prior to
Reserved
Upper 128 Byte Lock (UL) — R/WLO.
0 = Bytes not locked.
1 = Bytes 38h-3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be
Lower 128 Byte Lock (LL) — R/WLO.
0 = Bytes not locked.
1 = Bytes 38h-3Fh in the lower 128-byte bank of RTC RAM are locked and cannot be
Upper 128 Byte Enable (UE) — R/W.
0 = Bytes locked.
1 = The upper 128-byte bank of RTC RAM can be accessed.
Reserved
I/O port F0h write. It will also drive IGNNE# active.
accessed. Writes will be dropped and reads will not return any assured data. Bit
reset on system reset.
accessed. Writes will be dropped and reads will not return any assured data. Bit
reset on system reset.
access to the IOxAPIC address range.
00h
00000000h
®
ICH8 generates IRQ13 internally and holds it until an
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
8-bit
R/W, R/WLO
32-bit
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