NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 349

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
9.2.7
Intel
®
ICH8 Family Datasheet
DMACH_MODE—DMA Channel Mode Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
7:6
3:2
1:0
Bit
5
4
DMA Transfer Mode — WO. Each DMA channel can be programmed in one of four
different modes:
00 = Demand mode
01 = Single mode
10 = Reserved
11 = Cascade mode
Address Increment/Decrement Select — WO. This bit controls address increment/
decrement during DMA transfers.
0 = Address increment. (default after part reset or Master Clear)
1 = Address decrement.
Autoinitialize Enable — WO.
0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count.
1 = DMA restores the Base Address and Count registers to the current registers
DMA Transfer Type — WO. These bits represent the direction of the DMA transfer.
When the channel is programmed for cascade mode, (bits[7:6] = 11) the transfer type
is irrelevant.
00 = Verify – No I/O or memory strobes generated
01 = Write – Data transferred from the I/O devices to memory
10 = Read – Data transferred from memory to the I/O device
11 = Invalid
DMA Channel Select — WO. These bits select the DMA Channel Mode Register that
will be written by bits [7:2].
00 = Channel 0 (4)
01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)
A part reset or Master Clear disables autoinitialization.
following a terminal count (TC).
Ch. #0
Ch. #4
0000 00xx
No
–
–
3 = 0Bh;
7 = D6h
Description
Attribute:
Size:
Power Well:
WO
8-bit
Core
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