NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 401

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
9.8.3.9
9.8.3.10
9.8.3.11
Intel
®
ICH8 Family Datasheet
LV5—Level 5 Register (Mobile Only)
I/O Address:
Default Value:
Lockable:
NOTE: This register should not be used by IA-64 processors or systems with more than 1 logical processor,
LV6—Level 6 Register (Mobile Only)
I/O Address:
Default Value:
Lockable:
NOTE: This register should not be used by IA-64 processors or systems with more than 1 logical
PM2_CNT—Power Management 2 Control (Mobile Only)
I/O Address:
Default Value:
Lockable:
Power Well:
7:0
7:0
7:1
Bit
Bit
Bit
0
unless appropriate semaphoring software has been put in place to ensure that all threads/processors
are ready for the C5 state when the read to this register occurs.
processor, unless appropriate semaphoring software has been put in place to ensure that
all threads/processors are ready for the C6 state when the read to this register occurs.
Reads to this register return all 0’s, writes to this register have no effect. Reads to this
register generate a “enter a C5 power state” to the clock control logic. The C5 state
persists until a break event occurs.
Reads to this register return all 0’s, writes to this register have no effect. Reads to this
register generate a “enter a C6 power state” to the clock control logic. The C6 state
persists until a break event occurs.
Reserved
Arbiter Disable (ARB_DIS) — R/W This bit is essentially just a scratchpad bit for
legacy software compatibility. Software typically sets this bit to 1 prior to entering a C3
or C4 state. When a transition to a C3 or C4 state occurs, ICH8 will automatically
prevent any internal or external non-Isoch bus masters from initiating any cycles up to
the (G)MCH. This blocking starts immediately upon the ICH8 sending the Go-C3
message to the (G)MCH. The blocking stops when the Ack-C2 message is received.
Note that this is not really blocking, in that messages (such as from PCI Express*) are
just queued and held pending.
PMBASE + 17h (ACPI P_BLK + 7)
00h
No
PMBASE + 18h (ACPI P_BLK + 8)
00h
No
PMBASE + 20h
(ACPI PM2_BLK)
00h
No
Core
Description
Description
Description
Attribute:
Size:
Usage:
Power Well:
Attribute:
Size:
Usage:
Power Well:
Attribute:
Size:
Usage:
RO
8-bit
ACPI or Legacy
Core
RO
8-bit
ACPI or Legacy
Core
R/W
8-bit
ACPI
401