NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 396

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.8.3.2
396
PM1_EN—Power Management 1 Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
13:11
7:6
4:1
Bit
15
14
10
9
8
5
0
Reserved
PCI Express* Wake Disable(PCIEXPWAK_DIS) — R/W. Modification of this bit has
no impact on the value of the PCIEXP_WAKE_STS bit.
0 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register enabled to wake
1 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register disabled from
Reserved
RTC Event Enable (RTC_EN) — R/W. This bit is in the RTC well to allow an RTC event
to wake after a power failure. This bit is not cleared by any reset other than RTCRST#
or a Power Button Override event.
0 = No SCI (or SMI#) or wake event is generated then RTC_STS (PMBASE + 00h, bit
1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit
Reserved.
Power Button Enable (PWRBTN_EN) — R/W. This bit is used to enable the setting
of the PWRBTN_STS bit to generate a power management event (SMI#, SCI).
PWRBTN_EN has no effect on the PWRBTN_STS bit (PMBASE + 00h, bit 8) being set by
the assertion of the power button. The Power Button is always enabled as a Wake
event.
0 = Disable.
1 = Enable.
Reserved.
Global Enable (GBL_EN) — R/W. When both the GBL_EN and the GBL_STS bit
(PMBASE + 00h, bit 5) are set, an SCI is raised.
0 = Disable.
1 = Enable SCI on GBL_STS going active.
Reserved.
Timer Overflow Interrupt Enable (TMROF_EN) — R/W. Works in conjunction with
the SCI_EN bit (PMBASE + 04h, bit 0) as described below:
TMROF_EN
the system.
waking the system
10) goes active.
goes active.
0
1
1
PMBASE + 02h
(ACPI PM1a_EVT_BLK + 2)
0000h
No
Bits 0
Bits 8
Bit 10: RTC
–
–
SCI_EN
7: Core,
9, 11
X
0
1
–
15: Resume,
Effect when TMROF_STS is set
Description
No SMI# or SCI
SMI#
SCI
Attribute:
Size:
Usage:
LPC Interface Bridge Registers (D31:F0)
R/W
16-bit
ACPI or Legacy
Intel
®
ICH8 Family Datasheet