NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 685

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Intel
17.2.29
17.2.30
17.2.31
Intel
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ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
RIRBSTS—RIRB Status Register
(Intel
Memory Address:HDBAR + 5Dh
Default Value:
RIRBSIZE—RIRB Size Register
(Intel
Memory Address:HDBAR + 5Eh
Default Value:
IC—Immediate Command Register
(Intel
Memory Address:HDBAR + 60h
Default Value:
31:0
7:3
7:4
3:2
1:0
Bit
Bit
Bit
2
1
0
Reserved.
Response Overrun Interrupt Status — R/WC. Software sets this bit to 1 when the
RIRB DMA engine is not able to write the incoming responses to memory before
additional incoming responses overrun the internal FIFO. When the overrun occurs, the
hardware will drop the responses which overrun the buffer. An interrupt may be
generated if the Response Overrun Interrupt Control bit is set. Note that this status bit
is set even if an interrupt is not enabled for this event.
Software clears this bit by writing a 1 to it.
Reserved.
Response Interrupt — R/WC. Hardware sets this bit to 1 when an interrupt has been
generated after N number of Responses are sent to the RIRB buffer OR when an empty
Response slot is encountered on all SDI[x] inputs (whichever occurs first). Note that
this status bit is set even if an interrupt is not enabled for this event.
Software clears this bit by writing a 1 to it.
RIRB Size Capability — RO. Hardwired to 0100b indicating that the ICH8 only supports
a RIRB size of 256 RIRB entries (2048B).
Reserved.
RIRB Size — RO. Hardwired to 10b which sets the CORB size to 256 entries (2048B).
Immediate Command Write — R/W. The command to be sent to the codec via the
Immediate Command mechanism is written to this register. The command stored in this
register is sent out over the link during the next available frame after a 1 is written to
the ICB bit (HDBAR + 68h: bit 0).
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High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
00h
42h
00000000h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/WC
8 bits
RO
8 bits
R/W
32 bits
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