NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 577

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UHCI Controllers Registers
Intel
®
ICH8 Family Datasheet
Bit
2
1
0
Global Reset (GRESET) — R/W.
0 = This bit is reset by the software after a minimum of 10 ms has elapsed as specified
1 = Global Reset. The host controller sends the global reset signal on the USB and then
Host Controller Reset (HCRESET) — R/W. The effects of HCRESET on Hub registers
are slightly different from Chip Hardware Reset and Global USB Reset. The HCRESET
affects bits [8,3:0] of the Port Status and Control Register (PORTSC) of each port.
HCRESET resets the state machines of the host controller including the Connect/
Disconnect state machine (one for each port). When the Connect/Disconnect state
machine is reset, the output that signals connect/disconnect are negated to 0,
effectively signaling a disconnect, even if a device is attached to the port. This virtual
disconnect causes the port to be disabled. This disconnect and disabling of the port
causes bit 1 (connect status change) and bit 3 (port enable/disable change) of the
PORTSC to get set. The disconnect also causes bit 8 of PORTSC to reset. About 64 bit
times after HCRESET goes to 0, the connect and low-speed detect will take place, and
bits 0 and 8 of the PORTSC will change accordingly.
0 = Reset by the host controller when the reset process is complete.
1 = Reset. When this bit is set, the host controller module resets its internal timers,
Run/Stop (RS) — R/W. When set to 1, the ICH8 proceeds with execution of the
schedule. The ICH8 continues execution as long as this bit is set. When this bit is
cleared, the ICH8 completes the current transaction on the USB and then halts. The HC
Halted bit in the status register indicates when the host controller has finished the
transaction and has entered the stopped state. The host controller clears this bit when
the following fatal errors occur: consistency check failure, PCI Bus errors.
0 = Stop
1 = Run
NOTE: This bit should only be cleared if there are no active Transaction Descriptors in
in Chapter 7 of the USB Specification.
resets all its logic, including the internal hub registers. The hub registers are reset
to their power on state. Chip Hardware Reset has the same effect as Global Reset
(bit 2), except that the host controller does not send the Global Reset on USB.
counters, state machines, etc. to their initial value. Any transaction currently in
progress on USB is immediately terminated.
the executable schedule or software will reset the host controller prior to setting
this bit again.
Description
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