NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 726

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

726
17:15
14:8
6:3
Bit
7
2
1
0
Common Clock Exit Latency (CCEL) — R/W. This value represents the L0s Exit
Latency for common-clock configurations (LCTL.CCC = 1) (D28:F0/F1/F2/F3/F4/
F5:Offset 50h:bit 6). It defaults to 128 ns to less than 256 ns, but may be overridden
by BIOS.
Reserved
Port I/OxApic Enable (PAE) — R/W.
0 = Hole is disabled.
1 = A range is opened through the bridge for the following memory addresses:
Reserved
Bridge Type (BT) — RO. This register can be used to modify the Base Class and
Header Type fields from the default PCI-to-PCI bridge to a Host Bridge. Having the root
port appear as a Host Bridge is useful in some server configurations.
0 = The root port bridge type is a PCI-to-PCI Bridge, Header Sub-Class = 04h, and
1 = The root port bridge type is a PCI-to-PCI Bridge, Header Sub-Class = 00h, and
Hot Plug SMI Enable (HPME) — R/W.
0 = Disable. SMI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SMI whenever a Hot-Plug event is detected.
Power Management SMI Enable (PMME) — R/W.
0 = Disable. SMI generation based on a power management event is disabled.
1 = Enables the root port to generate SMI whenever a power management event is
Port #
1
2
3
4
5
6
Header Type = Type 1.
Header Type = Type 0.
detected.
FEC1_0000h – FEC1_7FFFh
FEC2_0000h – FEC2_7FFFh
FEC3_0000h – FEC3_7FFFh
FEC1_8000h – FEC1_FFFFh
FEC2_8000h – FEC2_FFFFh
FEC3_8000h – FEC3_FFFFh
Address
Description
PCI Express* Configuration Registers
Intel
®
ICH8 Family Datasheet