NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 280

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NH82801HBM S LB9A

Manufacturer Part Number
NH82801HBM S LB9A
Description
CONTROLLER HUB, ICH8M, I/O, 82801HBM
Manufacturer
Intel
Datasheet

Specifications of NH82801HBM S LB9A

Power Dissipation Pd
2.4W
Digital Ic Case Style
BGA
No. Of Pins
676
Pci Bus Type
I/O Controller Hub
Pci Express Base Spec
PCIe 1.1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
7.1.34
7.1.35
7.1.36
280
LCTL—Link Control Register
Offset Address: 01A8–01A9h
Default Value:
LSTS—Link Status Register
Offset Address: 01AA–01ABh
Default Value:
CIR2 — Chipset Initialization Register 2
Offset Address: 01F4–01F7h
Default Value:
(Desktop
(Mobile
15:10
Only)
Only)
31:0
15:8
9:4
3:0
Bit
Bit
6:2
1:0
1:0
Bit
7
Reserved
Negotiated Link Width (NLW) — RO. Negotiated link width is x4 (000100b).
ICH8M may also indicate x2 (000010b), depending on (G)MCH configuration.
Link Speed (LS) — RO. Link is 2.5 Gb/s.
CIR2 Field 1 — R/W. BIOS shall program to 86000040h
Reserved
Extended Synch (ES) — R/W. When set, forces extended transmission of FTS
ordered sets when exiting L0s prior to entering L0.
Reserved
Reserved
Active State Link PM Control (APMC) — R/W. Indicates whether DMI should
enter L0s.
00 = Disabled
01 = L0s entry enabled
10 = Reserved
11 = Reserved
0000h
0041h
00000000h
Description
Description
Description
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Chipset Configuration Registers
R/W
16-bit
RO
16-bit
R/W
32-bit
Intel
®
ICH8 Family Datasheet

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