NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 424

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.10.1
9.10.2
424
GPIO_USE_SEL—GPIO Use Select Register
Offset Address: GPIOBASE + 00h
Default Value:
Lockable:
GP_IO_SEL—GPIO Input/Output Select Register
Offset Address: GPIOBASE +04h
Default Value:
Lockable:
31:0
Bit
31:0
Bit
GPIO_USE_SEL[31:0] — R/W. Each bit in this register enables the corresponding
GPIO (if it exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
NOTES:
1.
2.
3.
4.
5.
6.
GP_IO_SEL[31:0] — R/W. When configured in native mode (GPIO_USE_SEL[n] is
0), writes to these bits have no effect. The value reported in this register is undefined
when programmed as native mode.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
The following bits are always 1 because they are unmultiplexed: 8, 18, 20. The
following bits are also unmultiplexed in desktop configuration: 12, 13, 16
If GPIO[n] does not exist, then the bit in this register will always read as 0 and
writes will have no effect.
When RSMRST# is asserted, all multiplexed signals in the resume and core
wells are configured as their default function. When just PLTRST# is asserted,
the GPIO in the core well are configured as their default function.
When configured to GPIO mode, the multiplexing logic will present the inactive
state to native logic that uses the pin as an input.
All GPIOs are reset to the default state by CF9h reset except GPIO24
If the GPIO use is configured by a soft strap, the corresponding bit in this
register is ignored. This applies to the following ICH8M bits: [13:12].
197F75FFh (Desktop)
197E55FFh (Mobile)
No
E0EA7FFFh
No
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/W
32-bit
Core for 0:7, 16:23,
Resume for 8:15, 24:31
R/W
32-bit
Core for 0:7, 16:23,
Resume for 8:15, 24:31
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ICH8 Family Datasheet