NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 268

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.1.1
7.1.2
7.1.3
268
VCH—Virtual Channel Capability Header Register
Offset Address: 0000–0003h
Default Value:
VCAP1—Virtual Channel Capability #1 Register
Offset Address: 0004–0007h
Default Value:
VCAP2—Virtual Channel Capability #2 Register
Offset Address: 0008–000Bh
Default Value:
31:20
19:16
31:12
11:10
31:24
15:0
23:8
9:8
6:4
2:0
7:0
Bit
Bit
Bit
7
3
Next Capability Offset (NCO) — RO. Indicates the next item in the list.
Capability Version (CV) — RO. Indicates support as a version 1 capability structure.
Capability ID (CID) — RO. Indicates this is the Virtual Channel capability item.
Reserved
Port Arbitration Table Entry Size (PATS) — RO. Indicates the size of the port
arbitration table is 4 bits (to allow up to 8 ports).
Reference Clock (RC) — RO. Fixed at 100 ns.
Reserved
Low Priority Extended VC Count (LPEVC) — RO. Indicates that there are no additional
VCs of low priority with extended capabilities.
Reserved
Extended VC Count (EVC) — RO. Indicates that there is one additional VC (VC1) that
exists with extended capabilities.
VC Arbitration Table Offset (ATO) — RO. Indicates that no table is present for VC
arbitration since it is fixed.
Reserved
VC Arbitration Capability (AC) — RO. Indicates that the VC arbitration is fixed in the
root complex.
10010002h
00000000h
00000001h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Chipset Configuration Registers
RO
32-bit
RO
32-bit
RO
32-bit
Intel
®
ICH8 Family Datasheet