NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 715

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express* Configuration Registers
18.1.29
Intel
®
ICH8 Family Datasheet
LCTL—Link Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 50h-51h
Default Value:
15:8
1:0
Bit
7
6
5
4
3
2
Reserved
Extended Synch (ES) — R/W.
0 = Extended synch disabled.
1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from
Common Clock Configuration (CCC) — R/W.
0 = The ICH8 and device are not using a common reference clock.
1 = The ICH8 and device are operating with a distributed common reference clock.
Retrain Link (RL) — WO.
0 = This bit always returns 0 when read.
1 = The root port will train its downstream link.
NOTE: Software uses LSTS.LT (D28:F0/F1/F2/F3/F4/F5:52, bit 11) to check the status
Link Disable (LD) — R/W.
0 = Enabled.
1 = The root port will disable the link.
Read Completion Boundary Control (RCBC) — RO. this bit indicates the read
completion boundary is 64 bytes.
Reserved
Active State Link PM Control (APMC) — R/W. This field indicates whether the root
port should enter L0s or L1 or both.
L1 prior to entering L0.
Bits
00b
01b
10b
11b
of training.
0000h
Disabled
L0s Entry is Enabled
L1 Entry is Enabled
L0s and L1 Entry Enabled
Definition
Description
Attribute:
Size:
R/W, WO, RO
16 bits
715