NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 397

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
9.8.3.3
Intel
®
ICH8 Family Datasheet
PM1_CNT—Power Management 1 Control
I/O Address:
Default Value:
Lockable:
Power Well:
(Desktop
(Mobile
31:14
12:10
Only)
Only)
9:3
Bit
13
2
1
1
0
Reserved.
Sleep Enable (SLP_EN) — WO. Setting this bit causes the system to sequence into
the Sleep state defined by the SLP_TYP field.
Sleep Type (SLP_TYP) — R/W. This 3-bit field defines the type of Sleep the system
should enter when the SLP_EN bit is set to 1. These bits are only reset by RTCRST#.
Reserved.
Global Release (GBL_RLS) — WO.
0 = This bit always reads as 0.
1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software
Reserved
Bus Master Reload (BM_RLD) — R/W. This bit is treated as a scratchpad bit. This
bit is reset to 0 by PLTRST#
0 = Bus master requests will not cause a break from the C3 state.
1 = Enable Bus Master requests (internal, external or BMBUSY#) to cause a break
If software fails to set this bit before going to C3 state, ICH8 will still return to a
snoopable state from C3 or C4 states due to bus master activity.
SCI Enable (SCI_EN) — R/W. Selects the SCI interrupt or the SMI# interrupt for
various events including the bits in the PM1_STS register (bit 10, 8, 0), and bits in
GPE0_STS.
0 = These events will generate an SMI#.
1 = These events will generate an SCI.
Code
000b
001b
010b
011b
100b
101b
110b
111b
has a corresponding enable and status bits to control its ability to receive ACPI
events.
from the C3 state.
PMBASE + 04h
(ACPI PM1a_CNT_BLK)
00000000h
No
Bits 0
Bits 8
Bits 13
Master Interrupt
ON: Typically maps to S0 state.
Asserts STPCLK#. Puts processor in Stop-Grant state. Optional to
assert CPUSLP# to put processor in sleep state: Typically maps to S1
state.
Reserved
Reserved
Reserved
Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state.
Suspend-To-Disk. Assert SLP_S3#, and SLP_S4#: Typically maps to S4
state.
Soft Off. Assert SLP_S3#, SLP_S4#, and SLP_S5#: Typically maps to
S5 state.
–
–
7: Core,
12: RTC,
–
15: Resume
Description
Attribute:
Size:
Usage:
R/W, WO
32-bit
ACPI or Legacy
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