NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 721

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express* Configuration Registers
18.1.36
18.1.37
18.1.38
Intel
®
ICH8 Family Datasheet
MID—Message Signaled Interrupt Identifiers Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 80h–81h
Default Value:
MC—Message Signaled Interrupt Message Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 82–83h
Default Value:
MA—Message Signaled Interrupt Message Address
Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 84h
Default Value:
15:8
15:8
31:2
7:0
6:4
3:1
1:0
Bit
Bit
Bit
7
0
Next Pointer (NEXT) — RO. Indicates the location of the next pointer in the list.
Capability ID (CID) — RO. Capabilities ID indicates MSI.
Reserved
64 Bit Address Capable (C64) — RO. Capable of generating a 32-bit message only.
Multiple Message Enable (MME) — R/W. These bits are R/W for software
compatibility, but only one message is ever sent by the root port.
Multiple Message Capable (MMC) — RO. Only one message is required.
MSI Enable (MSIE) — R/W.
0 = Disabled.
1 = MSI is enabled and traditional interrupt pins are not used to generate interrupts.
NOTE: CMD.BME (D28:F0/F1/F2/F3/F4/F5:04h:bit 2) must be set for an MSI to be
Address (ADDR) — R/W. This field provides the lower 32 bits of the system specified
message address, always DW aligned.
Reserved
generated. If CMD.BME is cleared, and this bit is set, no interrupts (not even pin
based) are generated.
9005h
0000h
00000000h
–
87h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
16 bits
R/W, RO
16 bits
R/W
32 bits
721