NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 247

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.23.2.3
5.23.3
5.23.3.1
Table 97.
Intel
®
ICH8 Family Datasheet
The following is a list of additional requirements specific to configurations 2 and 3:
Device Requirements for GbE
A serial flash device that will be used for both system BIOS and GbE on the same
device must meet the minimum compatibility requirements detailed in
Serial Flash Command Set
Required Command Set for Interoperability
The following table contains a list of commands and the associated opcodes that a SPI-
based serial flash device must support in order to be interoperable with the Intel Serial
Peripheral Interface.
Required Commands and Opcodes
Write Status
Program Data
Read Data
Write Disable
Read Status
Write Enable
Fast Read
Enable Write
Status
Erase
JEDEC ID
• 4 Kbytes erase size must be supported.
• Flash device must power up in an unlocked state (no write protection) or use the
• Byte write must be supported.
• A serial flash device that requires the Write Enable command must automatically
• Status Register bit 0 must be set to 1 when a write or erase is in progress and
• Minimum density of AFSC + BIOS is 8 Mb
• Minimum density of ASF + BIOS is 8 Mb
• Minimum density of Intel
Commands
write status register to disable write protection. If the write status register must be
unprotected, it must use the enable write status register command 50h or write
enable 06h. Opcode 01h must then be used to write 00h into the write status
register. This must unlock the entire part. If there is no need to write enable the
write status register, then 06h and 50h must be ignored.
clear the Write Enable Latch at the end of Data Program instructions.
cleared to 0 when a write or erase is NOT in progress.
Minimum density of Intel AMT 2.5 (Mobile Only) + BIOS +GbE is 32 Mb.
— The flexibility to perform a write between 1 byte to 256 bytes is recommended
Programmab
OPCODE
04h
06h
0Bh
50h
01h
02h
03h
05h
9Fh
le
®
If command is supported, 01h must be the opcode.
Write Data / Program Data
If command is supported, 06h must be the opcode.
If Write status register must be unlocked it must use this
opcode or Write Enable.
Size and opcode programmed in the VSSC Register
Refer to
AMT 2.0 (Desktop Only)+BIOS+GbE is 16 Mb;
Section 5.23.3.3
Notes
Section 5.23.2.1
247