MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet
MOD5234-100IR
Specifications of MOD5234-100IR
Related parts for MOD5234-100IR
MOD5234-100IR Summary of contents
Page 1
MCF5235 Reference Manual Devices Supported: MCF5232 MCF5233 MCF5234 MCF5235 Document Number: MCF5235RM Rev. 2 07/2006 ...
Page 2
How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland ...
Page 3
Enhanced Multiply-Accumulate Unit (EMAC) Chip Configuration Module (CCM) Reset Controller Module System Control Module (SCM) General Purpose I/O Module Interrupt Controller Modules Edge Port Module (EPORT) External Interface Module (EIM) Synchronous DRAM Controller Fast Ethernet Controller (FEC) Enhanced Time Processing ...
Page 4
Overview 2 Signal Descriptions 3 ColdFire Core 4 Enhanced Multiply-Accumulate Unit (EMAC) 5 Cache 6 Static RAM (SRAM) 7 Clock Module 8 Power Management Chip Configuration Module (CCM) 9 Reset Controller Module 10 11 System Control Module (SCM) 12 ...
Page 5
Paragraph Number 1.1 MCF5235 Family Configurations ................................................................................... 1-2 1.2 Block Diagram ................................................................................................................ 1-3 1.3 Features ........................................................................................................................... 1-5 1.3.1 Feature Overview ........................................................................................................ 1-5 1.3.2 V2 Core Overview ...................................................................................................... 1-9 1.3.3 Enhanced Time Processor Unit (eTPU) ...................................................................... 1-9 1.3.3.1 eTPU Functions .................................................................................................... ...
Page 6
Paragraph Number 2.2 Signal Properties Summary ............................................................................................ 2-3 2.3 Signal Primary Functions ................................................................................................ 2-8 2.3.1 Reset Signals ............................................................................................................... 2-8 2.3.2 PLL and Clock Signals ............................................................................................... 2-9 2.3.3 Mode Selection ........................................................................................................... 2-9 2.3.4 External Memory Interface Signals ............................................................................ 2-9 2.3.5 SDRAM ...
Page 7
Paragraph Number 3.5 Exception Processing Overview ..................................................................................... 3-9 3.6 Exception Stack Frame Definition ................................................................................ 3-11 3.7 Processor Exceptions .................................................................................................... 3-13 3.7.1 Access Error Exception ............................................................................................ 3-13 3.7.2 Address Error Exception ........................................................................................... 3-13 3.7.3 Illegal Instruction Exception ..................................................................................... 3-13 3.7.4 Divide-By-Zero ...
Page 8
Paragraph Number 5.1 Introduction ..................................................................................................................... 5-1 5.1.1 Features ....................................................................................................................... 5-1 5.1.2 Physical Organization ................................................................................................. 5-1 5.1.3 Operation .................................................................................................................... 5-3 5.1.3.1 Interaction with Other Modules .............................................................................. 5-3 5.1.3.2 Memory Reference Attributes ................................................................................ 5-4 5.1.3.3 Cache Coherency and Invalidation ......................................................................... 5-4 5.1.3.4 ...
Page 9
Paragraph Number 7.1.3.5 Low-power Mode Operation .................................................................................. 7-6 7.2 External Signal Descriptions .......................................................................................... 7-6 7.2.1 EXTAL ....................................................................................................................... 7-7 7.2.2 XTAL .......................................................................................................................... 7-7 7.2.3 CLKOUT .................................................................................................................... 7-7 7.2.4 CLKMOD[1:0] ........................................................................................................... 7-7 7.2.5 RSTOUT ..................................................................................................................... 7-7 7.3 Memory Map/Register Definition .................................................................................. 7-8 ...
Page 10
Paragraph Number 8.2.1 Register Descriptions .................................................................................................. 8-1 8.2.1.1 Low-Power Interrupt Control Register (LPICR) .................................................... 8-2 8.2.1.2 Low-Power Control Register (LPCR) .................................................................... 8-3 8.3 Functional Description .................................................................................................... 8-4 8.3.1 Low-Power Modes ...................................................................................................... 8-4 8.3.1.1 Run Mode ............................................................................................................... 8-5 8.3.1.2 Wait Mode ...
Page 11
Paragraph Number 9.1.2 Features ....................................................................................................................... 9-1 9.1.3 Modes of Operation .................................................................................................... 9-2 9.2 External Signal Descriptions .......................................................................................... 9-2 9.2.1 RCON ......................................................................................................................... 9-2 9.2.2 CLKMOD[1:0] ........................................................................................................... 9-2 9.2.3 D[25:24, 21:19, 16] (Reset Configuration Override) ................................................. 9-3 9.3 Memory Map/Register Definition .................................................................................. ...
Page 12
Paragraph Number 10.4.1.6 Software Reset ...................................................................................................... 10-6 10.4.2 Reset Control Flow ................................................................................................... 10-6 10.4.2.1 Synchronous Reset Requests ................................................................................ 10-8 10.4.2.2 Internal Reset Request .......................................................................................... 10-8 10.4.2.3 Power-On Reset .................................................................................................... 10-8 10.4.3 Concurrent Resets ..................................................................................................... 10-8 10.4.3.1 Reset Flow ............................................................................................................ 10-8 ...
Page 13
Paragraph Number 12.1.1 Overview ................................................................................................................... 12-3 12.1.2 Features ..................................................................................................................... 12-3 12.2 External Signal Description .......................................................................................... 12-3 12.3 Memory Map/Register Definition .............................................................................. 12-10 12.3.1 Register Descriptions .............................................................................................. 12-12 12.3.1.1 Port Output Data Registers (PODR_ 12.3.1.2 Port Data Direction Registers (PDDR_ 12.3.1.3 ...
Page 14
Paragraph Number 14.1 Introduction ................................................................................................................... 14-1 14.1.1 Overview ................................................................................................................... 14-1 14.1.2 Features ..................................................................................................................... 14-2 14.2 DMA Transfer Overview .............................................................................................. 14-3 14.3 Memory Map/Register Definition ................................................................................ 14-4 14.3.1 DMA Request Control (DMAREQC) ...................................................................... 14-5 14.3.2 Source Address Registers (SAR0–SAR3) ................................................................ 14-6 ...
Page 15
Paragraph Number 16.1 Introduction ................................................................................................................... 16-1 16.1.1 Overview ................................................................................................................... 16-1 16.2 External Signal Description .......................................................................................... 16-1 16.2.1 Chip Selects (CS[7:0]) .............................................................................................. 16-1 16.2.2 Output Enable (OE) .................................................................................................. 16-1 16.2.3 Byte Strobes (BS[3:0]) .............................................................................................. 16-2 16.3 Chip Select Operation ................................................................................................... 16-3 ...
Page 16
Paragraph Number 17.7 Misaligned Operands .................................................................................................. 17-16 Synchronous DRAM Controller Module 18.1 Introduction ................................................................................................................... 18-1 18.1.1 Block Diagram .......................................................................................................... 18-1 18.1.2 Overview ................................................................................................................... 18-3 18.1.2.1 Definitions ............................................................................................................ 18-3 18.1.3 Operation .................................................................................................................. 18-3 18.2 External Signal Description .......................................................................................... 18-4 18.3 Memory ...
Page 17
Paragraph Number 19.1.5 Interface Options ....................................................................................................... 19-4 19.1.5.1 10 Mbps and 100 Mbps MII Interface .................................................................. 19-4 19.1.5.2 10 Mpbs 7-Wire Interface Operation .................................................................... 19-5 19.1.6 Address Recognition Options ................................................................................... 19-5 19.1.7 Internal Loopback ..................................................................................................... 19-5 19.2 Memory Map/Register Definition ...
Page 18
Paragraph Number 19.3.3 Microcontroller Initialization .................................................................................. 19-36 19.3.4 User Initialization (After Asserting ECRn[ETHER_EN]) ..................................... 19-37 19.3.5 Network Interface Options ...................................................................................... 19-37 19.3.6 FEC Frame Transmission ....................................................................................... 19-38 19.3.7 FEC Frame Reception ............................................................................................. 19-39 19.3.8 Ethernet Address Recognition ................................................................................ 19-40 19.3.9 ...
Page 19
Paragraph Number 20.6.2 Register Description ............................................................................................... 20-16 20.6.2.1 System Configuration Registers ......................................................................... 20-16 20.6.2.2 Time Base Registers ........................................................................................... 20-23 20.6.2.3 Global Channel Registers ................................................................................... 20-27 20.6.2.4 Channel Configuration and Control Registers .................................................... 20-33 20.7 Functional Description ................................................................................................ 20-39 20.8 Initialization/Application ...
Page 20
Paragraph Number 21.4.5.1 Serial Message Buffers (SMBs) ......................................................................... 21-27 21.4.5.2 Message Buffer Deactivation ............................................................................. 21-27 21.4.5.3 Locking and Releasing Message Buffers ........................................................... 21-28 21.4.6 CAN Protocol Related Frames ............................................................................... 21-29 21.4.6.1 Remote Frames ................................................................................................... 21-29 21.4.6.2 Overload Frames ................................................................................................. 21-29 ...
Page 21
Paragraph Number 23.3.4 Interrupt Operation ................................................................................................... 23-7 24.1 Introduction ................................................................................................................... 24-1 24.1.1 Overview ................................................................................................................... 24-1 24.1.2 Features ..................................................................................................................... 24-2 24.2 Memory Map/Register Definition ................................................................................ 24-2 24.2.1 Prescaler .................................................................................................................... 24-2 24.2.2 Capture Mode ........................................................................................................... 24-3 24.2.3 Reference Compare ................................................................................................... 24-3 24.2.4 ...
Page 22
Paragraph Number 25.2.4 Transfer Length ......................................................................................................... 25-8 25.2.5 Data Transfer ............................................................................................................ 25-8 25.3 Memory Map/Register Definition ................................................................................ 25-9 25.3.1 QSPI Mode Register (QMR) .................................................................................... 25-9 25.3.2 QSPI Delay Register (QDLYR) ............................................................................. 25-11 25.3.3 QSPI Wrap Register (QWR) ................................................................................... 25-12 25.3.4 ...
Page 23
Paragraph Number 26.4.3 Looping Modes ....................................................................................................... 26-24 26.4.3.1 Automatic Echo Mode ........................................................................................ 26-24 26.4.3.2 Local Loop-Back Mode ...................................................................................... 26-24 26.4.3.3 Remote Loop-Back Mode ................................................................................... 26-25 26.4.4 Multidrop Mode ...................................................................................................... 26-25 26.4.5 Bus Operation ......................................................................................................... 26-27 26.4.5.1 Read Cycles ........................................................................................................ 26-27 ...
Page 24
Paragraph Number Message Digest Hardware Accelerator (MDHA) 28.1 Introduction ................................................................................................................... 28-1 28.1.1 Overview ................................................................................................................... 28-1 28.1.2 Features ..................................................................................................................... 28-1 28.1.3 Modes of Operation .................................................................................................. 28-3 28.2 Memory Map/Register Definition ................................................................................ 28-3 28.2.1 MDHA Mode Register (MDMR) ............................................................................. 28-4 28.2.1.1 Invalid ...
Page 25
Paragraph Number Random Number Generator (RNG) 29.1 Introduction ................................................................................................................... 29-1 29.1.1 Overview ................................................................................................................... 29-1 29.2 Memory Map/Register Definition ................................................................................ 29-1 29.2.1 RNG Control Register (RNGCR) ............................................................................. 29-1 29.2.2 RNG Status Register (RNGSR) ................................................................................ 29-3 29.2.3 RNG Entropy Register (RNGER) ............................................................................. ...
Page 26
Paragraph Number 30.2.1.12 SKHA Context Registers (SKCR 30.3 Functional Description ................................................................................................ 30-16 30.3.1 Transmit FIFO Interface Block ............................................................................... 30-17 30.3.2 Receive FIFO Interface Block ................................................................................ 30-17 30.3.3 Top Control Block .................................................................................................. 30-17 30.3.4 SKHA Logic Block ................................................................................................. 30-17 30.3.4.1 Address ...
Page 27
Paragraph Number 31.4.3.3 SAMPLE Instruction ............................................................................................ 31-9 31.4.3.4 SAMPLE/PRELOAD Instruction ....................................................................... 31-10 31.4.3.5 ENABLE_TEST_CTRL Instruction .................................................................. 31-10 31.4.3.6 HIGHZ Instruction .............................................................................................. 31-10 31.4.3.7 CLAMP Instruction ............................................................................................ 31-10 31.4.3.8 BYPASS Instruction ........................................................................................... 31-10 31.4.3.9 ACCESS_AUX_TAP_eTPU Instruction .......................................................... 31-11 31.5 Initialization/Application Information ...
Page 28
Paragraph Number 32.7 Processor Status, DDATA Definition ......................................................................... 32-44 32.7.1 User Instruction Set ................................................................................................ 32-44 32.7.2 Supervisor Instruction Set ....................................................................................... 32-48 32.8 Inter-debug and Cross-Triggering Support ................................................................. 32-49 32.9 Recommended BDM Pinout ....................................................................................... 32-50 32.10 eTPU Debug Programming Model ............................................................................. ...
Page 29
About This Book The primary objective of this reference manual is to define the functionality of the MCF5235 processor for use by software and hardware developers. In addition, this manual supports the MCF5232, MCF5233, and MCF5234. This book is written ...
Page 30
About This Book • Chapter 5, “Cache,” describes the MCF5235 cache implementation, including organization, configuration, and coherency. It describes cache operations and how the cache interacts with other memory structures. • Chapter 6, “Static RAM implementation. It covers general operations, ...
Page 31
Chapter 19, “Fast Ethernet Controllers (FEC0 & a functional block diagram, and transceiver connection information for both MII (Media Independent Interface) ...
Page 32
About This Book • Chapter 31, “IEEE 1149.1 Test Access Port operation of the MCF5235 Joint Test Action Group (JTAG) implementation. It describes those items required by the IEEE 1149.1 standard and provides additional information specific to the MCF5235. For ...
Page 33
Addenda/errata to reference manuals—Because some processors have follow-on parts, an addendum is provided that describes the additional features and functionality changes. Also, if mistakes are found within a reference manual, an errata document will be issued before the next ...
Page 34
About This Book ~ NOT logical operator & AND logical operator | OR logical operator Acronyms and Abbreviations Table i lists acronyms and abbreviations used in this document. Table i. Acronyms and Abbreviated Terms Term ADC Analog-to-digital conversion ALU Arithmetic ...
Page 35
Table i. Acronyms and Abbreviated Terms (Continued) Term Mux Multiplex NOP No operation OEP Operand execution pipeline PC Program counter PCLK Processor clock PLIC Physical layer interface controller PLL Phase-locked loop POR Power-on reset PQFP Plastic quad flat pack PWM ...
Page 36
About This Book Table ii. Notational Conventions (Continued) Instruction An Any address register n (example address register 3) Ay,Ax Source and destination address registers, respectively Dn Any data register n (example data register 5) Dy,Dx Source ...
Page 37
Table ii. Notational Conventions (Continued) Instruction # <vector> Identifies the 4-bit vector number for trap instructions <> identifies an indirect data address referencing memory <xxx> identifies an absolute address referencing memory dn Signal displacement value, n bits wide (example: d16 ...
Page 38
About This Book Table ii. Notational Conventions (Continued) Instruction {} Optional operation () Identifies an indirect address d Displacement value, n-bits wide (example Address Calculated effective address (pointer) Bit Bit selection (example: Bit 3 of D0) lsb Least ...
Page 39
Table iii. MCF5235RM Revision History (Continued) Location — Changes are noted in revision 1.7 or later of the MCF5235RMAD document. Freescale Semiconductor Substantive Changes Revision 2, 07/2006 MCF5235 Reference Manual, Rev. 2 Revision History xxxix ...
Page 40
About This Book xl MCF5235 Reference Manual, Rev. 2 Freescale Semiconductor ...
Page 41
Chapter 1 Overview The MCF5235 is a family of highly-integrated 32-bit microcontrollers based on the V2 ColdFire microarchitecture. Featuring channel eTPU, 64 Kbytes of internal SRAM, a 2-block SDRAM controller, four 32-bit timers with DMA request ...
Page 42
Overview • Clock module with integrated phase locked loop (PLL) • External bus interface module including a 2-block synchronous DRAM controller • 32-bit non-multiplexed bus with chip select signals that support paged mode Flash memories To locate ...
Page 43
Table 1-1. MCF5235 Family Configurations (Continued) Module JTAG - IEEE 1149.1 Test Access Port Package 1.2 Block Diagram The superset device in the MCF5235 family comes in a 256 mold array process ball grid array (MAPBGA) package. Figure 1-1 Freescale ...
Page 44
Overview FAST ETHERNET (To/From PADI) CONTROLLER (FEC) (To/From PADI DMA (To/From PADI) DREQ[2:0] DACK[2:0] JTAG_EN NEXUS JTAG TAP eTPU (To/From PADI) Watchdog Timer SKHA FlexCAN RNGA MDHA Cryptography Modules 1-4 (To/From SRAM backdoor) INTC0 INTC1 Arbiter UART UART ...
Page 45
Features 1.3.1 Feature Overview • Version 2 ColdFire variable-length RISC processor core — Static operation — 32-bit address and data path on-chip — Processor core runs at twice the internal bus frequency — Sixteen general-purpose 32-bit data and address ...
Page 46
Overview — 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA, FEC) • Fast Ethernet Controller (FEC) — 10 BaseT capability, half duplex or full duplex — 100 BaseT capability, half duplex or ...
Page 47
Modem support includes request-to-send (UnRTS) and clear-to-send (UnCTS) lines for two UARTs — Transmit and receive FIFO buffers • Module 2 — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads — Fully compatible with ...
Page 48
Overview — Separate clock output pins • Interrupt Controllers (x2) — Support for up to 110 interrupt sources per interrupt controller organized as follows: – 103 fully-programmable interrupt sources – 7 fixed-level interrupt sources — Seven external interrupt signals — ...
Page 49
Sets boot device and its data port width — Configures output pad drive strength — Unique part identification number and part revision number — Reset – Separate reset in and reset out signals – Six sources of reset: Power-on ...
Page 50
Overview intervention. Consequently, the host CPU setup and service times for each timer event are minimized or eliminated. The eTPU is an enhanced version of the TPU module implemented on the MC68332 and MPC500 products. Enhancements of the eTPU include ...
Page 51
AnglePulse – Output signal based on angle 1.3.3.1.3 Set 3 (Motor Control 1) • All functions from set 1 • DC – DC motor with permanent magnet • DCE – DC motor with separately excited stator windings • BLDC ...
Page 52
Overview captured operand data, and branch target addresses defining processor activity at the CPU’s clock rate. The integration of the eTPU on the MCF5235 family marks the first time that ColdFire and eTPU debug subsystems have been present in a ...
Page 53
For all data cache configurations, the memory operates in write-through mode and all operand writes generate an external bus cycle. 1.3.6.2 SRAM The SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core can access in a ...
Page 54
Overview 2 1.3. Bus The I C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data 2 exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications ...
Page 55
Clock Module and Phase Locked Loop (PLL) The clock module contains a crystal oscillator (OSC), phase-locked loop (PLL), reduced frequency divider (RFD), status/control registers, and control logic. To improve noise immunity, the PLL and OSC have their own power ...
Page 56
Overview 1.3.20 SDRAM Controller The SDRAM controller provides all required signals for glueless interfacing to a variety of JEDEC-compliant SDRAM devices. SRAS/SCAS address multiplexing is software configurable for different page sizes. To maintain refresh capability without conflicting with concurrent accesses ...
Page 57
Documentation Documentation is available from a local Freescale distributor, a Freescale sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com/coldfire. Freescale Semiconductor MCF5235 Reference Manual, Rev. 2 Documentation 1-17 ...
Page 58
Overview 1-18 MCF5235 Reference Manual, Rev. 2 Freescale Semiconductor ...
Page 59
Chapter 2 Signal Descriptions 2.1 Introduction This chapter describes MCF5235 signals. It includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state at reset, and identifies whether a pull-up resistor should be ...
Page 60
Signal Descriptions RCON Chip CLKMOD0 Configuration CLKMOD1 RESET Reset Controller RSTOUT TEA BS[3:0] OE External Interface 2 TSIZ[1:0] Module R/W TIP 32 D[31:0] 24 A[23:0] Chip 8 CS[7:0] Selects IRQ[7:1] Edgeport 2 SD_CS[1:0] SD_WE SD_SRAS SDRAM Controller ...
Page 61
Signal Properties Summary Table 2-16 lists the MCF5235 signals grouped by functionality. In this table and throughout this document a single signal within a group is designated without square brackets (i.e., A24), while designations for multiple signals within a ...
Page 62
Signal Descriptions Table 2-1. MCF523x Signal Information and Muxing (Continued) Alternate Signal Name GPIO 1 A[20:0] — — D[31:16] — — D[15:8] PDATAH[7:0] — D[7:0] PDATAL[7:0] — BS[3:0] PBS[7:4] CAS[3:0] OE PBUSCTL7 — TA PBUSCTL6 — TEA PBUSCTL5 DREQ1 R/W ...
Page 63
Table 2-1. MCF523x Signal Information and Muxing (Continued) Alternate Signal Name GPIO 1 CS1 PCS1 — CS0 — — SD_WE PSDRAM5 — SD_SCAS PSDRAM4 — SD_SRAS PSDRAM3 — SD_CKE PSDRAM2 — SD_CS[1:0] PSDRAM[1:0 — ] IRQ[7:3] PIRQ[7:3] — IRQ2 PIRQ2 ...
Page 64
Signal Descriptions Table 2-1. MCF523x Signal Information and Muxing (Continued) Alternate Signal Name GPIO 1 TCRCLK PETPU2 — UTPUODIS PETPU1 — LTPUODIS PETPU0 — EMDIO PFECI2C2 I2C_SDA EMDC PFECI2C3 I2C_SCL ECOL — — ECRS — — ERXCLK — — ERXDV ...
Page 65
Table 2-1. MCF523x Signal Information and Muxing (Continued) Alternate Signal Name GPIO 1 QSPI_CLK PQSPI2 I2C_SCL QSPI_DIN PQSPI1 I2C_SDA QSPI_DOUT PQSPI0 — U2TXD PUARTH1 CAN1TX U2RXD PUARTH0 CAN1RX U1CTS PUARTL7 U2CTS U1RTS PUARTL6 U2RTS U1TXD PUARTL5 CAN0TX U1RXD PUARTL4 CAN0RX ...
Page 66
Signal Descriptions Table 2-1. MCF523x Signal Information and Muxing (Continued) Alternate Signal Name GPIO 1 DDATA[3:0] — — PST[3:0] — — TEST — — PLL_TEST — — VDDPLL — — VSSPLL — — OVDD — — VSS — — VDD ...
Page 67
Signal Name Abbreviation Reset In RESET Reset Out RSTOUT 2.3.2 PLL and Clock Signals Table 2-3 describes signals that are used to support the on-chip clock generation circuitry. Signal Name Abbreviation External Clock In EXTAL Crystal XTAL Clock Out CLKOUT ...
Page 68
Signal Descriptions Table 2-5. External Memory Interface Signals Signal Name Abbreviation Address Bus A[23:0] Data Bus D[31:0] Byte Strobes BS[3:0] Output Enable OE Transfer Acknowledge TA Transfer Error TEA Acknowledge Read/Write R/W Transfer Size TSIZ[1:0] Transfer Start TS 2-10 Function ...
Page 69
Table 2-5. External Memory Interface Signals (Continued) Signal Name Abbreviation Transfer in Progress TIP Chip Selects CS[7:0] 2.3.5 SDRAM Controller Signals Table 2-6 describes signals that are used for SDRAM accesses. Table 2-6. SDRAM Controller Signals Signal Name Abbreviation SDRAM ...
Page 70
Signal Descriptions Signal Name Abbreviation TCRCLK TCRCLK TPUCH[31:0] TPUCH[31:0] Channel pins for the eTPU module. They can also be configured for LTPUODIS LTPUODIS UTPUDIS UTPUDIS 2.3.8 Ethernet Module (FEC) Signals The following signals are used by the Ethernet module for ...
Page 71
Table 2-9. Ethernet Module (FEC) Signals (Continued) Signal Name Abbreviation Receive Data 0 ERXD0 Carrier Receive Sense ECRS Transmit Data 1–3 ETXD[3:1] Transmit Error ETXER Receive Data 1–3 ERXD[3:1] Receive Error ERXER 2.3.9 Feature Control Signal Name Abbreviation eTPU/Ethernet Enable ...
Page 72
Signal Descriptions 2.3.11 Queued Serial Peripheral Interface (QSPI) Table 2-12 describes QSPI signals. Table 2-12. Queued Serial Peripheral Interface (QSPI) Signals Signal Name Abbreviation QSPI Syncrhonous QSPI_DOUT Serial Output QSPI Synchronous QSPI_DIN Serial Data Input QSPI Serial Clock QSPI_CLK Synchronous ...
Page 73
Table 2-13. UART Module Signals (Continued) Signal Name Abbreviation Clear-to-Send U1CTS/U0CTS Indicate to the UART modules that they can begin data transmission. Request-to-Send U1RTS/U0RTS Automatic request-to-send outputs from the UART modules. 2.3.13 DMA Timer Signals Table 2-14 describes the signals ...
Page 74
Signal Descriptions Signal Name Abbreviation Test Reset TRST Test Clock TCLK Test Mode Select TMS Test Data Input TDI Test Data Output TDO Development Serial DSCLK Clock Breakpoint BKPT Development Serial DSI Input Development Serial DSO Output Debug Data DDATA[3:0] ...
Page 75
Table 2-16. Processor Status (Continued) PST[3:0] 1001 1010 1011 1100 1101 1110 1111 2.3.15 Test Signals Table 2-17 describes test signals. Signal Name Abbreviation Test TEST PLL Test PLL_TEST 2.3.16 Power and Ground Pins The pins described in Table 2-18 ...
Page 76
Signal Descriptions default to their bus functionalities as shown in listed in Table 2-16 will operate as described above. All other signals will default to GPIO inputs. Table 2-19. Default Signal Functions After System Reset (External Boot Mode) Signal A[23:0] ...
Page 77
Chapter 3 ColdFire Core This section describes the organization of the Version 2 (V2) ColdFire overview of the program-visible registers. For detailed information on instructions, see the ColdFire Family Programmer’s Reference Manual. 3.1 Processor Pipelines Figure 3 block ...
Page 78
ColdFire Core which decodes the instruction, fetches the required operands and then executes the required function. Since the IFP and OEP pipelines are decoupled by an instruction buffer which serves as a FIFO queue, the IFP is able to prefetch ...
Page 79
Address Registers (A0–A6) These registers can be used as software stack pointers, index registers, or base address registers; they can also be used for word and longword operations. 3.2.1.3 Stack Pointer (A7) Certain ColdFire implementations, including the MCF5235, support ...
Page 80
ColdFire Core 3.2.1.5 Condition Code Register (CCR) The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results generated by processor operations. Bit 4, the extend bit (X bit), is also used ...
Page 81
One 32-bit status register (MACSR) including four indicator bits signaling product or accumulation overflow (one for each accumulator: PAV0–PAV3) These registers are shown in 31:24 3.2.3 Supervisor Register Description Only system control software is intended to use the supervisor ...
Page 82
ColdFire Core Table 3-3. Supervisor Programming Model 31:24 The following paragraphs describe the supervisor programming model registers. 3.2.3.1 Status Register (SR) The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control bits. In ...
Page 83
Supervisor/User Stack Pointers (A7 and OTHER_A7) The MCF5235 architecture supports two independent stack pointer (A7) registers stack pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two programmable-visible 32-bit registers does not identify one as ...
Page 84
ColdFire Core 3.2.3.5 Access Control Registers (ACR0, ACR1) The access control registers, ACR0 and ACR1, define attributes for two user-defined memory regions. These attributes include the definition of cache mode, write protect, and buffer write enables. The ACRs are described ...
Page 85
Table 3-5. ColdFire CPU Registers (Continued) Name CPU Space (Rc) RAMBAR 3.4 Additions to the Instruction Set Architecture The original ColdFire instruction set architecture (ISA) was derived from the M68000-family opcodes based on extensive analysis of embedded application code. After ...
Page 86
ColdFire Core All ColdFire processors use an instruction restart exception model, but certain microarchitectures (V2 and V3) require more software support to recover from certain access errors. See Section 3.7.1, “Access Error Exception processing includes all actions from the detection ...
Page 87
Table 3-7. Exception Vector Assignments (Continued) Vector Number( 6– 15–23 24 25–31 32–47 48–63 64–255 “Fault” refers to the PC of the instruction that caused the exception; “Next” refers to ...
Page 88
ColdFire Core 31 SSP FORMAT + 0x4 Figure 3-5. Exception Stack Frame Form The 16-bit format/vector word contains 3 unique fields: • A 4-bit format field at the top of the system stack is always written with a value of ...
Page 89
Processor Exceptions 3.7.1 Access Error Exception The exact processor response to an access error depends on the type of memory reference being performed. For an instruction fetch, the processor postpones the error reporting until the faulted reference is needed ...
Page 90
ColdFire Core 10 and 11, respectively. The V2 core does not provide illegal instruction detection on the extension words on any instruction, including MOVEC. 3.7.4 Divide-By-Zero Attempting to divide by zero causes an exception (vector 5, offset = 0x014). 3.7.5 ...
Page 91
Unimplemented Line-A Opcode A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is generated by the attempted execution of an undefined line-A opcode. 3.7.8 Unimplemented Line-F Opcode A line-F opcode is defined when ...
Page 92
ColdFire Core 3.7.13 Fault-on-Fault Halt If a ColdFire processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic “fault-on-fault” condition. A reset is required to force the processor to ...
Page 93
R W Reset MAC DIV EMAC FPU MMU W Reset Figure 3-6. D0 Hardware Configuration Info Table 3-10. D0 Hardware Configuration Info Field Description Bits ...
Page 94
ColdFire Core Table 3-10. D0 Hardware Configuration Info Field Description (Continued) Bits Name 7–4 ISA Instruction set architecture (ISA) revision number. 0000 ISA_A 0001 ISA_B 0010 ISA_C 1000 ISA_A+ (ISA_A with the addition of the BYTEREV, BITREV, FF1, and STLDSR ...
Page 95
Table 3-11. D1 Local Memory Hardware Configuration Information Field Description Bits Name 13–12 DCA Data cache associativity. 00 Four-way. 01 Direct mapped. (This is the value used for MCF5235) 11–8 DCSIZ Data cache size. 0000 No data cache. (This is ...
Page 96
ColdFire Core 3. The OEP completes all memory accesses without any stall conditions caused by the memory itself. Thus, the timing details provided in this section assume that an infinite zero-wait state memory is attached to the processor core. 4. ...
Page 97
Table 3-13. Move Byte and Word Execution Times (Continued) Source Rx (xxx).l 3(1/0) (d ,PC) 3(1/ ,PC,Xi) 4(1/0) 8 #<xxx> 1(0/0) Table 3-14. Move Long Execution Times Source Rx Dn 1(0/0) An 1(0/0) (An) 2(1/0) (An)+ 2(1/0) -(An) ...
Page 98
ColdFire Core Table 3-15. One Operand Instruction Execution Times (Continued) Opcode <EA> Rn ext.w Dx 1(0/0) ext.l Dx 1(0/0) extb.l Dx 1(0/0) ff1 Dx 1(0/0) neg.l Dx 1(0/0) negx.l Dx 1(0/0) not.l Dx 1(0/0) scc Dx 1(0/0) stldsr #imm — ...
Page 99
Table 3-16. Two Operand Instruction Execution Times (Continued) Opcode <EA> Rn bset Dy,<ea> 2(0/0) bset #imm,<ea> 2(0/0) btst Dy,<ea> 2(0/0) btst #imm,<ea> 1(0/0) cmp.l <ea>,Rx 1(0/0) cmpi.l #imm,Dx 1(0/0) 1 divs.w <ea>,Dx 20(0/0) 1 divu.w <ea>,Dx 20(0/0) 1 ≤35(0/0) ≤38(1/0) ...
Page 100
ColdFire Core 3.11 Miscellaneous Instruction Execution Times Table 3-17. Miscellaneous Instruction Execution Times Opcode <EA> Rn link.w Ay,#imm 2(0/1) move.w CCR,Dx 1(0/0) move.w <ea>,CC 1(0/0) R move.w SR,Dx 1(0/0) move.w <ea>,SR 7(0/0) movec Ry,Rc 9(0/1) movem.l <ea>,&list — movem.l &list,<ea> ...
Page 101
Table 3-18. EMAC Instruction Execution Times (Continued) Opcode <EA> muls.l <ea>y, Dx mulu.l <ea>y, Dx mac.w Ry, Rx, Raccx mac.l Ry, Rx, Raccx msac.w Ry, Rx, Raccx msac.l Ry, Rx, Raccx mac.w Ry, Rx, <ea>, Rw, Raccx mac.l Ry, Rx, ...
Page 102
ColdFire Core The execution times for moving the contents of the Racc, Raccext[01,23], MACSR, or Rmask into a destination location <ea>x shown in this table represent the best-case scenario when the store instruction is executed and there are no load ...
Page 103
BITREV Bit Reversed Dx → Dx Operation: Assembler Syntax: BITREV.L Dx Attributes: Size = longword Instruction Format The contents of the destination data register are bit-reversed; that is, new Dx[31] = old Dx[0], new ...
Page 104
ColdFire Core BYTEREV Byte Reversed Dx → Dx Operation: Assembler Syntax: BYTEREV.L Dx Attributes: Size = longword Instruction Format The contents of the destination data register are byte-reversed as defined below: Condition Codes: Not ...
Page 105
FF1 Bit Offset of the First Logical One in Register → Destination Operation: Assembler Syntax: FF1.L Dx Attributes: Size = longword Instruction Format The data register, Dx, is scanned, beginning from the most-significant bit ...
Page 106
ColdFire Core STRLDSR Operation: If Supervisor State Then → SP; zero-filled SR → (SP); immediate data → SR Else TRAP Assembler Syntax:STRLDSR #<data> Attributes: Size = word Instruction Format ...
Page 107
Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC) This chapter describes the functionality, microarchitecture, and performance of the enhanced multiply-accumulate (EMAC) unit in the ColdFire family of processors. 4.1 Multiply-Accumulate Unit The MAC design provides a set of DSP operations which can ...
Page 108
Enhanced Multiply-Accumulate Unit (EMAC) Figure 4-1. Multiply-Accumulate Functionality Diagram 4.2 Introduction to the MAC The MAC is an extension of the basic multiplier found in most microprocessors typically implemented in hardware within an architecture and supports rapid execution ...
Page 109
General Operation The MAC speeds execution of ColdFire integer multiply instructions (MULS and MULU) and provides additional functionality for multiply-accumulate operations. By executing ...
Page 110
Enhanced Multiply-Accumulate Unit (EMAC) Product 40 Extended Product + Accumulator Extension Byte Upper [7:0] Product Extended Product + Accumulator Extension Byte Upper [7:0] Figure 4-5. Signed and Unsigned Integer Alignment Thus, the 48-bit accumulator definition is a function of the ...
Page 111
MACSR[6:5] == -1/* signed fractional mode */ Complete Accumulator [47:0] = {ACCextn[15:8], ACCn[31:0], ACCextn[7:0]} if MACSR[6:5] == 10/* unsigned integer mode */ Complete Accumulator[47:0] = {ACCextn[15:0], ACCn[31:0]} The four accumulators are represented as an array, ACCn, where n selects ...
Page 112
Enhanced Multiply-Accumulate Unit (EMAC) 4.4 Memory Map/Register Definition The EMAC provides the following program-visible registers: • Four 32-bit accumulators (ACCn = ACC0, ACC1, ACC2, and ACC3) • Eight 8-bit accumulator extensions (two per accumulator), packaged as two 32-bit values for ...
Page 113
Table 4-1. MACSR Field Descriptions Bits Name 31–12 — Reserved, should be cleared. 11–8 PAVx Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past MAC or MSAC instructions generated an overflow during product calculation or the ...
Page 114
Enhanced Multiply-Accumulate Unit (EMAC) Table 4-1. MACSR Field Descriptions (Continued) Bits Name 4 R/T Round/truncate mode. Controls the rounding procedure for MOV.L ACCx,Rx, or MSAC.L instructions when operating in fractional mode. 0 Truncate. The product’s lsbs are dropped before it ...
Page 115
Table 4-2. Summary of S/U, F/I, and R/T Control Bits S/U F/I R 4.4.1.1 Fractional Operation Mode This section describes behavior when the fractional mode is used (MACSR[F/I] is set). 4.4.1.1.1 Rounding When the ...
Page 116
Enhanced Multiply-Accumulate Unit (EMAC) — If the lsb of R0 and R0.L =0x8000, the number is rounded down. This method minimizes rounding bias and creates as statistically correct an answer as possible. The rounding algorithm is summarized in ...
Page 117
EMAC_state_restore: movem.l (a7),#0x00ff move.l #0,macsr move.l d0,acc0 move.l d1,acc1 move.l d2,acc2 move.l d3,acc3 move.l d4,accext01 move.l d5,accext23 move.l d6,mask move.l d7,macsr By executing this type of sequence, the exact state of the EMAC programming model can be correctly saved and ...
Page 118
Enhanced Multiply-Accumulate Unit (EMAC) if extension word, bit [ the MASK bit, then if <ea> = (An & {0xFFFF, MASK} if <ea> = (An ( & {0xFFFF, MASK} ...
Page 119
Table 4-3. EMAC Instruction Summary (Continued) Command Load AccExtensions23 MOV.L {Ry,#imm},ACCext23 Store AccExtensions01 MOV.L ACCext01,Rx Store AccExtensions23 MOV.L ACCext23,Rx 4.5.1 EMAC Instruction Execution Times The instruction execution times for the EMAC can be found in Execution Times.” The EMAC execution ...
Page 120
Enhanced Multiply-Accumulate Unit (EMAC) In Figure 4-8, the OEP stalls the store-accumulator instruction for 3 cycles: the depth of the EMAC pipeline minus 1. The minus 1 factor is needed because the OEP and EMAC pipelines overlap by a cycle, ...
Page 121
The overflow (V) flag is handled differently set if the complete product cannot be represented as a 40-bit value (this applies to 32 × 32 integer operations only the combination of the product with an ...
Page 122
Enhanced Multiply-Accumulate Unit (EMAC) else operandX[31:0] = {sign-extended Rx[15], Rx[15:0]} } else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31: perform the multiply */ product[63:0] = operandY[31:0] * operandX[31:0] /* check for product overflow */ if ((product[63:39] != 0x0000_00_0) && ...
Page 123
MACSR (MACSR.OMC == transfer the result to the accumulator */ ACCx[47:0] = result[47:0] } MACSR.V = MACSR.PAVx MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR else MACSR ((ACCx[47:31] ...
Page 124
Enhanced Multiply-Accumulate Unit (EMAC) /* check for accumulation overflow */ if (accumulationOverflow == 1) then {MACSR.PAVx = 1 MACSR (MACSR.OMC == transfer the result to the accumulator */ ACCx[47:0] = result[47:0] } MACSR.V = ...
Page 125
} /* zero-fill to 48 bits before performing any scaling */ product[47:40 scale product before combining with accumulator */ switch (SF) { case 0: break; case 1: product[40:0] = {product[39:0], 0} break; case 2: break; case 3: ...
Page 126
Enhanced Multiply-Accumulate Unit (EMAC) 4-20 MCF5235 Reference Manual, Rev. 2 Freescale Semiconductor ...
Page 127
Chapter 5 Cache 5.1 Introduction This chapter describes the MCF5235 cache operation. 5.1.1 Features • Configurable as instruction, data, or split instruction/data cache • 8-Kbyte direct-mapped cache • Single-cycle access on cache hits • Physically located on the Coldfire core's ...
Page 128
Cache If the desired address is mapped into the cache memory, the output of the storage array is driven onto the ColdFire core's local data bus, thereby completing the access in a single cycle. The tag array maintains a single ...
Page 129
Local Address Bus 5.1.3 Operation The cache is physically connected to the ColdFire core's local bus, allowing it to service all fetches from the ColdFire core and certain memory fetches initiated by the debug module. Typically, ...
Page 130
Cache 5.1.3.2 Memory Reference Attributes For every memory reference the ColdFire core or the debug module generates, a set of “effective attributes” is determined based on the address and the access control registers (ACRs). This set of attributes includes the ...
Page 131
Reset A hardware reset clears the CACR and disables the cache. The contents of the tag array are not affected by the reset. Accordingly, the system startup code must explicitly perform a cache invalidation by setting CACR[CINV] before the ...
Page 132
Cache line-fill buffer versus its corresponding cache location. At the time of the miss, the hardware indicator is set, marking the line-fill buffer as “most recently used.” subsequent access occurs to the cache location defined by bits [12:4] ...
Page 133
Addresses not assigned to the registers and undefined register bits are reserved for future expansion. The user should write zeros to these reserved address spaces and read accesses will return zeros. • The reset value column indicates the register ...
Page 134
Cache Bits Name 31 CENB Cache enable. The memory array of the cache is enabled only if CENB is asserted. This bit, along with the DISI (disable instruction caching) and DISD (disable data caching) bits, control the cache configuration. 0 ...
Page 135
Table 5-4. CACR Field Descriptions (Continued) Bits Name 21 INVI CINV instruction cache only. This bit can not be set unless the cache configuration is split (both DISI and DISD cleared). For instruction or data cache configurations this bit is ...
Page 136
Cache Table 5-5 shows the relationship between CACR bits CENB, DISI, & DISD and the cache configuration. Table 5-5. Cache Configuration as Defined by CACR CACR CACR CACR [CENB] [DISI] [DISD ...
Page 137
IPSBAR space cannot be cached. Ensure that ACR[AB] does not fall within this space Reset Reset Address Figure ...
Page 138
Cache Table 5-7. ACR Field Descriptions (Continued) Bits Name 5 BWE Buffered write enable. This bit defines the value for enabling buffered writes. If BWE = 0, the termination of an operand write cycle on the processor's local bus is ...
Page 139
Chapter 6 Static RAM (SRAM) 6.1 Introduction This chapter is a description of the on-chip static RAM (SRAM) implementation that covers general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using ...
Page 140
Static RAM (SRAM) 6.2.1 SRAM Base Address Register (RAMBAR) The configuration information in the SRAM base address register (RAMBAR) controls the operation of the SRAM module. • The RAMBAR holds the base address of the SRAM. The MOVEC instruction provides ...
Page 141
Table 6-1. RAMBAR Field Descriptions (Continued) Bits Name 11–10 PRI1 Priority bit. PRI1 determines if DMA/FEC or CPU has priority in upper 32k bank of memory. PRI0 PRI0 determines if DMA/FEC or CPU has priority in lower 32k bank of ...
Page 142
Static RAM (SRAM) 6.2.2 SRAM Initialization After a hardware reset, the contents of the SRAM module are undefined. The valid bit of the RAMBAR is cleared, disabling the module. If the SRAM requires initialization with instructions or data, the following ...
Page 143
Power Management As noted previously, depending on the configuration defined by the RAMBAR, instruction fetch and operand read accesses may be sent to the SRAM and cache simultaneously. If the access is mapped to the SRAM module, it sources ...
Page 144
Static RAM (SRAM) 6-6 MCF5235 Reference Manual, Rev. 2 Freescale Semiconductor ...
Page 145
Chapter 7 Clock Module 7.1 Introduction The clock module allows the MCF5235 to be configured for one of several clocking methods. Clocking modes include internal frequency modulated phase-locked loop (PLL) clocking with either an external clock reference or an external ...
Page 146
Clock Module Throughout this manual, f refers to the internal bus frequency. Figure 7-1. MCF5235 Clock Connections PLL x2 PLLREF 0 1 XTAL Oscillator EXTAL 7.1.1 Block Diagram Figure 7-2 shows a block diagram of the entire clock module. The ...
Page 147
EXTAL XTAL External Clock OSC STPMD Stop Mode Figure 7-2. Clock Module Block Diagram Freescale Semiconductor CLKMOD[1:0] RSTOUT MFD PLLMODE Reference Clock PLL PLLREF LOCEN LOLRE CLKGEN PLLSEL DISCLK PLLMODE MCF5235 Reference Manual, Rev. 2 CLKOUT LOCKS LOCK LOCS RFD[2:0] ...
Page 148
Clock Module EXTAL OSC XTAL Bus Interface CLKMOD[1:0] 7.1.2 Features Features of the clock module include: • 25-MHz reference crystal oscillator • Current controlled oscillator range from 50 MHz to 150 MHz • Reduced frequency divider for reduced ...
Page 149
Normal PLL Mode with Crystal Reference In normal mode with a crystal reference, the PLL receives an input clock frequency from the crystal oscillator circuit and multiplies the frequency to create the PLL output clock. It can synthesize frequencies ...
Page 150
Clock Module output. Consequently, frequency modulation is not available. To enter external clock mode, the PLL must be set by following the procedure outlined in XTAL must be tied low in external clock mode when reset is asserted ...
Page 151
Table 7-2. Signal Properties (Continued) Name CLKMOD[1:0] RSTOUT 7.2.1 EXTAL This input is driven by an external clock except when used as a connection to the external crystal when using the internal oscillator. 7.2.2 XTAL This output is an internal ...
Page 152
Clock Module 7.3 Memory Map/Register Definition The clock module programming model consists of these registers: • Synthesizer control register (SYNCR), which defines clock operation • Synthesizer status register (SYNSR), which reflects clock status Table 7-4. Clock Module Memory Map IPSBAR ...
Page 153
Bits Name 31–27 Reserved 26–24 MFD[2:0] Multiplication factor divider. The MFD bits control the value of the divider in the PLL feedback loop. The value specified by the MFD bits establish the multiplication factor applied to the reference frequency. The ...
Page 154
Clock Module Table 7-5. SYNCR Field Descriptions (Continued) Bits Name 16 LOCRE Loss-of-clock reset enable. Determines how the system handles a loss-of-clock condition. When the LOCEN bit is clear, LOCRE has no effect. If the LOCS flag in SYNSR indicates ...
Page 155
Synthesizer Status Register (SYNSR) In the SYNSR, only the LOLF and LOCF flag bits are writeable. Writes to bits other than LOLF and LOCF have no effect Reset ...
Page 156
Clock Module Table 7-6. SYNSR Field Descriptions (Continued) Bits Name 7 PLLMODE Clock mode. This bit is determined at reset and indicates which clock mode the system is utilizing (see to configure the system clock mode during reset. 0 External ...
Page 157
Table 7-6. SYNSR Field Descriptions (Continued) Bits Name 1 CALDONE Calibration complete. This bit indicates whether the calibration sequence has been completed since the last time frequency modulation was enabled. If CALDONE = 0, the calibration sequence is either in ...
Page 158
Clock Module Table 7-8. Clock Out and Clock In Relationships System Clock Mode Normal PLL clock mode 1:1 PLL clock mode External clock mode input reference frequency ref f = CLKOUT frequency sys/2 MFD ranges from 0 ...
Page 159
External Reset Once POR for both the device and the VDDPLL supplies have negated, the PLL will begin its lock detect algorithm. However valid reference is not present, the PLL will continue to operate in SCM until ...
Page 160
Clock Module 5. Monitor the LOCK flag in SYNSR. When the PLL achieves lock, write the RFD value from step 1 to the RFD field of the SYNCR. This changes the system clocks frequency to the required frequency ...
Page 161
Write a value of RFD = RFD + 1 to the RFD field of the SYNCR to ensure the maximum system frequency is not exceeded during the calibration routine. 5. Program the desired modulation rates and depths to the ...
Page 162
Clock Module 7.4.5 Frequency Modulation Depth Calibration The frequency modulation calibration system tunes a reference current into the modulation D/A so that the modulation depth (F should be disabled prior to making a change to either the MFD, DEPTH, or ...
Page 163
D/A to update the calibration current. After obtaining the error count for the present iteration, both counters are cleared. The stored count of COUNT0 is preserved while a ...
Page 164
Clock Module For MFD=0,1: M=960. For MFD=2,3,4: M=480. For MFD=5,6,7: M=240. Figure 7-8. FM Auto-calibration Flow Chart 7-20 Enter Calibration Mode; Set PCALPASS=1 Count M reference clock cycles. Store value of feedback counter in CAL0. Enable FM. N=7. CAL[N] = ...
Page 165
PLL Operation In PLL mode, the PLL synthesizes the system clocks. The PLL can multiply the reference clock frequency 18x, provided that the system clock frequency remains within the range listed in the electrical specifications. For ...
Page 166
Clock Module reference EXTAL clock feedback Figure 7-10. Frequency Modulated PLL Block Diagram 7.4.6.1 Phase and Frequency Detector (PFD) The PFD is a dual-latch phase-frequency detector. It compares both the phase and frequency of the reference and feedback clocks. The ...
Page 167
Charge Pump/Loop Filter In 1:1 PLL mode, the charge pump uses a fixed current. In normal mode the current magnitude of the charge pump varies with the MFD as shown in Table 7-9. Charge Pump Current and MFD in ...
Page 168
Clock Module After lock is detected, the lock circuit continues to monitor the reference and feedback frequencies using the alternate count and compare process. If the counters do not match at any comparison time, then the LOCK flag is cleared ...
Page 169
MFD. If the PLL is intentionally disabled during stop mode, then after exit from stop mode, the LOCKS flag reflects the value prior to entering stop mode once lock is regained. 7.4.6.7 PLL Loss-of-Lock Reset If the LOLRE bit in ...
Page 170
Clock Module 7.4.6.11 Loss-of-Clock Interrupt Request When a loss-of-clock condition is detected, the PLL will request an interrupt if the LOCIRQ bit in the SYNCR is set. The LOCIRQ bit has no affect in external clock mode or if LOCEN ...
Page 171
Table 7-11. Stop Mode Operation (Sheet (Continued) MODE In NRM Off Off 0 Lose lock, f.b. clock, reference clock NRM Off Off 1 Lose lock, f.b. clock, reference clock NRM 0 ...
Page 172
Clock Module Table 7-11. Stop Mode Operation (Sheet (Continued) MODE In NRM NRM NRM Off X X Lose lock, f.b. clock, reference ...
Page 173
Table 7-11. Stop Mode Operation (Sheet (Continued) MODE In NRM Off On 1 Lose lock, f.b. clock NRM NRM NRM 1 0 ...
Page 174
Clock Module Table 7-11. Stop Mode Operation (Sheet (Continued) MODE In NRM NRM REF SCM ...
Page 175
Chapter 8 Power Management 8.1 Introduction This chapter explains the low-power operation of the MCF5235. 8.1.1 Features The following features support low-power operation. • Four modes of operation: Run, Wait, Doze, and Stop • Ability to shut down most peripherals ...
Page 176
Power Management 8.2.1.1 Low-Power Interrupt Control Register (LPICR) Implementation of low-power stop mode and exit from a low-power mode via an interrupt require communication between the CPU and logic associated with the interrupt controller. The LPICR is an 8-bit register ...
Page 177
R ENBSTOP W Reset 0 Address Figure 8-1. Low-Power Interrupt Control Register (LPICR) Bits Name 7 ENBSTOP Enable low-power stop mode. 0 Low-power stop mode disabled 1 Low-power stop mode enabled. Once the core is stopped and the signal ...
Page 178
Power Management Bits Name 7–6 LPMD Low-power mode select. Used to select the low-power mode the chip enters once the ColdFire CPU executes the STOP instruction. These bits must be written prior to instruction execution for them to take effect. ...
Page 179
An interrupt request whose priority is higher than the value programmed in the XLPM_IPL field of the LPICR. • An interrupt request whose priority higher than the value programmed in the interrupt priority mask (I) field of the core’s ...
Page 180
Power Management Entering stop mode will disable the SDRAMC including the refresh counter. If SDRAM is used, then code is required to insure proper entry and exit from stop mode. See Controller (SDRAMC)” for more information. 8.3.1.5 Peripheral Shut Down ...
Page 181
When stop mode is exited clearing the DCR[IS] bit will cause the SDRAM to exit the self-refresh mode and allow bus cycles to the SDRAM to resume. The SDRAM is inaccessible while in the self-refresh mode. Therefore, if stop mode ...
Page 182
Power Management setting of I2SR[IIF] signifies either the completion of one byte transfer or the reception of a calling address matching its own specified address when in slave receive mode stop mode, the I C Module stops immediately ...
Page 183
Fast Ethernet Controller (FEC) In wait and doze modes, the FEC may generate an interrupt to exit the low-power modes. • Clearing the ECNTRL[ETHER_EN] bit disables the FEC function. • The FEC is unaffected by wait mode and may ...
Page 184
Power Management 8.3.2.16 Clock Module In wait and doze modes, the clocks to the CPU and SRAM will be stopped and the system clocks to the peripherals are enabled. Each module may disable the module clocks locally at the module ...
Page 185
When this condition exists, the FlexCAN waits for all internal activity other than in the CAN bus interface to complete and then the following occurs: • The FlexCAN shuts down its clocks, stopping most of the ...
Page 186
Power Management 8.3.2.23 JTAG The JTAG (Joint Test Action Group) controller logic is clocked using the TCLK input and is not affected by the system clock. The JTAG cannot generate an event to cause the CPU to exit any low-power ...
Page 187
Table 8-5. CPU and Peripherals in Low-Power Modes (Continued) Module Programmable Interrupt Timers FlexCAN eTPU BDM JTAG 1 “Program” Indicates that the peripheral function during the low-power mode is dependent on programmable bits in the peripheral register map. 2 These ...
Page 188
Power Management 8-14 MCF5235 Reference Manual, Rev. 2 Freescale Semiconductor ...
Page 189
Chapter 9 Chip Configuration Module (CCM) 9.1 Introduction The Chip Configuration Module (CCM) controls the chip configuration and mode of operation for the MCF5235. 9.1.1 Block Diagram Figure 9-1. Chip Configuration Module Block Diagram 9.1.2 Features The CCM performs these ...
Page 190
Chip Configuration Module (CCM) • Selects low-power configuration • Selects transfer size function of the external bus • Selects processor status (PSTAT) and processor debug data (DDATA) functions • Selects BDM or JTAG mode 9.1.3 Modes of Operation The MCF5235 ...
Page 191
D[25:24, 21:19, 16] (Reset Configuration Override) If the external RCON pin is asserted during reset, then the states of these data pins during reset determine the chip mode of operation, boot device, clock mode, and certain module configurations after ...
Page 192
Chip Configuration Module (CCM CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2 See Chapter 8, “Power Management,” writes to this register. ...
Page 193
Table 9-4. CCR Field Descriptions (Continued) Bits Name 5 PSTEN PST[3:0]/DDATA[3:0] enable. This read/write bit enables the Processor Status (PST) and Debug Data (DDATA)n functions of the external pins. 0 PST/DDATA function disabled. 1 PST/DDATA function enabled. 4 — Reserved, ...
Page 194
Chip Configuration Module (CCM) Bits Name 15–10 — Reserved, should be cleared. 9–8 RCSC Chip select configuration. Reflects the default chip select configuration. The default function of the chip select configuration can be overridden during reset configuration. 7–6 — Reserved, ...
Page 195
Chip Identification Register (CIR Reset Address Figure 9-4. Chip Identification Register (CIR) Bits Name 15–6 PIN 5–0 PRN 9.4 Functional Description Six functions are defined within the chip configuration ...
Page 196
Chip Configuration Module (CCM) Table 9-7. Reset Configuration Pin States During Reset Pin D[25:24, 21:19, 16], RCON CLKMOD1, CLKMOD0 1 If the external RCON pin is not asserted during reset, pin functions are determined by the default operation mode defined ...
Page 197
Table 9-8. Configuration During Reset Pin(s) Affected Clock mode A[23:21]/CS[6:4] 1 Modifying the default configurations is possible only if the external RCON pin is asserted. 2 The D[31:26, 23:22, 18:17, 15:0] pins do not affect reset configuration. 3 The external ...
Page 198
Chip Configuration Module (CCM) 9.4.3 Boot Device Selection During reset configuration, the CS0 chip select pin is configured to select an external boot device. In this case, the V (valid) bit in the CSMR0 register is ignored, and CS0 is ...
Page 199
Chip Select Configuration The chip select configuration (CS[6:4]) is selected during reset and reflected in the RCSC field of the CCR. Once reset is exited, the chip select configuration cannot be changed. the different chip select configurations that can ...
Page 200
Chip Configuration Module (CCM) 9-12 MCF5235 Reference Manual, Rev. 2 Freescale Semiconductor ...