MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 26

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

30.2.1.12
30.3
30.3.1
30.3.2
30.3.3
30.3.4
30.3.4.1
30.3.4.2
30.3.4.3
30.3.5
30.4
30.4.1
30.4.2
31.1
31.1.1
31.1.2
31.1.3
31.2
31.2.1
31.2.2
31.2.3
31.2.4
31.2.5
31.2.6
31.3
31.3.1
31.3.1.1
31.3.1.2
31.3.1.3
31.3.1.4
31.3.1.5
31.4
31.4.1
31.4.2
31.4.3
31.4.3.1
31.4.3.2
xxvi
Paragraph
Number
Functional Description ................................................................................................ 30-16
Initialization/Application Information ........................................................................ 30-19
Introduction ................................................................................................................... 31-1
External Signal Description .......................................................................................... 31-3
Memory Map/Register Definition ................................................................................ 31-5
Functional Description .................................................................................................. 31-7
Transmit FIFO Interface Block ............................................................................... 30-17
Receive FIFO Interface Block ................................................................................ 30-17
Top Control Block .................................................................................................. 30-17
SKHA Logic Block ................................................................................................. 30-17
Security Assurance Features ................................................................................... 30-19
General Operation ................................................................................................... 30-19
Operation with Context Switch ............................................................................... 30-20
Block Diagram .......................................................................................................... 31-2
Features ..................................................................................................................... 31-2
Modes of Operation .................................................................................................. 31-3
JTAG Enable (JTAG_EN) ........................................................................................ 31-3
Test Clock Input (TCLK) ......................................................................................... 31-4
Test Mode Select/Breakpoint (TMS/BKPT) ............................................................. 31-4
Test Data Input/Development Serial Input (TDI/DSI) ............................................. 31-4
Test Reset/Development Serial Clock (TRST/DSCLK) .......................................... 31-4
Test Data Output/Development Serial Output (TDO/DSO) ..................................... 31-5
Register Descriptions ................................................................................................ 31-5
JTAG Module ........................................................................................................... 31-7
TAP Controller ......................................................................................................... 31-7
JTAG Instructions ..................................................................................................... 31-8
Address Decode Logic ........................................................................................ 30-18
Error Interrupt/Status Logic ................................................................................ 30-18
SKHA Core ......................................................................................................... 30-18
Instruction Shift Register (IR) .............................................................................. 31-5
IDCODE Register ................................................................................................. 31-5
Bypass Register .................................................................................................... 31-6
TEST_CTRL Register .......................................................................................... 31-6
Boundary Scan Register ....................................................................................... 31-7
EXTEST Instruction ............................................................................................. 31-9
IDCODE Instruction ............................................................................................. 31-9
SKHA Context Registers (SKCR
IEEE 1149.1 Test Access Port (JTAG)
MCF5235 Reference Manual, Rev. 2
Contents
Chapter 31
Title
n
) ................................................................... 30-15
Freescale Semiconductor
Number
Page