MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 743

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Ethernet
Freescale Semiconductor
address recognition 19-40
block diagram 19-2
buffer descriptors
collision handling 19-47
errors
frame reception 19-39
frame transmission 19-38
hash table 19-43
initialization 19-35
memory map 19-6
operation
registers
data direction (EPDDR) 15-4
flag (EPFR) 15-6
pin assignment (EPPAR) 15-3
pin data (EPPDR) 15-6
port data (EPDR) 15-5
port interrupt enable (EPIER) 15-5
receive (RxBD) 19-31
transmit (TxBD) 19-33
handling 19-48
reception
transmission
10 Mbps 7-Wire 19-5
10 Mbps and 100 Mbps MII 19-37
full duplex 19-4
half duplex 19-4
loopback 19-47
low-power modes 8-9
control (ECR) 19-13
descriptor group upper/lower address
descriptor individual upper/lower
descriptor individual upper/lower address
FIFO receive bound (FRBR) 19-25
FIFO receive start (FRSR) 19-26
FIFO transmit FIFO watermark (TFWR) 19-25
interrupt event (EIR) 19-9
interrupt mask (EIMR) 19-10
MIB control (MIBC) 19-17
CRC 19-49
frame length 19-49
non-octet 19-49
overrun 19-49
truncation 19-49
attempts limit expired 19-48
heartbeat 19-49
late collision 19-48
underrun 19-48
(GAUR/GALR) 19-24
(IAUR/IALR) 19-23
(IAUR/IALR) 19-22
,
19-46
,
19-37
MCF5235 Reference Manual, Rev. 2
eTPU
Exceptions
engine 20-5
memory map 20-14
registers
signals
access error 3-13
divide-by-zero 3-14
exception stack frame 3-11
format error 3-15
illegal instruction 3-13
MII management frame (MMFR) 19-14
MII speed control (MSCR) 19-16
opcode/pause duration (OPD) 19-21
physical address low (PALRn) 19-20
physical address low/high (PALR, PAUR) 19-20
receive buffer size (EMRBR) 19-28
receive control (RCR) 19-18
receive descriptor active (RDAR) 19-11
receive descriptor ring start (ERDSR) 19-27
transmit buffer descriptor ring start (ETSDR) 19-27
transmit control (TCR) 19-19
transmit descriptor active (TDAR) 19-12
channel data transfer request enable
channel data transfer request overflow status
channel data transfer request status
channel interrupt enable (ETPU_CIER) 20-30
channel interrupt overflow status
channel interrupt status (ETPU_CISR) 20-27
channel n configuration (ETPU_CnCR) 20-34
channel n host service request
channel n status control (ETPU_CnSCR) 20-36
channel pending service status
channel service status (ETPU_CSSR) 20-32
coherent dual-parameter controller
engine configuration (ETPU_ECR) 20-20
MISC compare (ETPU_MISCCMPR) 20-19
module configuration (ETPU_MCR) 20-16
time base 1 visibility (ETPU_TB1R) 20-25
time base 2 visibility (ETPU_TB2R) 20-26
time base configuration (ETPU_TBCR) 20-23
channel (TPUCH31–0) 20-13
channel output disable (LTPUODIS,
time base clock (TCRCLK) 20-13
(ETPU_CDTRER) 20-31
(ETPU_CDTROSR) 20-29
(ETPU_CDTRSR) 20-28
(ETPU_CIOSR) 20-28
(ETPU_CnHSRR) 20-39
(ETPU_CPSSR) 20-31
(ETPU_CDCR) 20-18
UTPUODIS) 20-13
–
20-8
Index-3