MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 523

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

There are two recommended methods of exiting wraparound mode: clearing QWR[WREN] or
setting QWR[HALT]. Exiting wraparound mode by clearing QDLYR[SPE] is not recommended
because this may abort a serial transfer in progress. The QSPI sets SPIF, clears QDLYR[SPE], and
stops the first time it reaches the end of the queue after QWR[WREN] is cleared. After
QWR[HALT] is set, the QSPI finishes the current transfer, then stops executing commands. After
the QSPI stops, QDLYR[SPE] can be cleared.
25.3 Memory Map/Register Definition
Table 25-3
25.3.1 QSPI Mode Register (QMR)
The QMR, shown in
Parameters such as QSPI_CLK polarity and phase, baud rate, master mode operation, and transfer
size are determined by this register. The data output high impedance enable, DOHIE, controls the
operation of QSPI_DOUT between data transfers. When DOHIE is cleared, QSPI_DOUT is
actively driven between transfers. When DOHIE is set, QSPI_DOUT assumes a high impedance
state.
Freescale Semiconductor
is the QSPI register memory map. Reading reserved locations returns zeros.
1
0x00_034C
0x00_0340
0x00_0344
0x00_0348
0x00_0350
0x00_0354
Because the QSPI does not operate in slave mode, the master mode
enable bit, QMR[MSTR], must be set for the QSPI module to operate
correctly.
Addresses not assigned to a register and undefined register bits are reserved for expansion.
Write accesses to these reserved address spaces and reserved register bits have no effect.
IPSBAR
Offset
Figure
QSPI Delay Register (QDLYR)
QSPI Address Register (QAR)
QSPI Interrupt Register (QIR)
QSPI Mode Register (QMR)
QSPI Wrap Register (QWR)
[31:24]
QSPI Data Register (QDR)
25-3, determines the basic operating modes of the QSPI module.
MCF5235 Reference Manual, Rev. 2
Table 25-3. QSPI Registers
[23:16]
NOTE
[15:8]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
1
1
1
1
1
Memory Map/Register Definition
[7:0]
25-9