MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 83

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

3.2.3.2
The MCF5235 architecture supports two independent stack pointer (A7) registers
stack pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two
programmable-visible 32-bit registers does not identify one as the SSP and the other as the USP.
Instead, the hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus,
the register contents are a function of the processor operation mode, as shown in the following:
if SR[S] = 1
The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It is the
responsibility of the external development system to determine, based on the setting of SR[S], the
mapping of A7 and OTHER_A7 to the two program-visible definitions (SSP and USP). This
functionality is enabled by setting the enable user stack pointer bit, CACR[EUSP]. If this bit is
cleared, only the stack pointer (A7), defined for previous ColdFire versions, is available. EUSP is
zero at reset.
If EUSP is set, the appropriate stack pointer register (SSP or USP) is accessed as a function of the
processor’s operating mode. To support dual stack pointers, the following two privileged M68000
instructions are added to the ColdFire instruction set architecture to load/store the USP:
These instructions are described in the ColdFire Family Programmer’s Reference Manual.
3.2.3.3
The VBR contains the base address of the exception vector table in memory. To access the vector
table, the displacement of an exception vector is added to the value in VBR. The lower 20 bits of
the VBR are not implemented by ColdFire processors; they are assumed to be zero, forcing the
table to be aligned on a 1 MByte boundary.
3.2.3.4
The CACR controls operation of the instruction/data cache memories. It includes bits for enabling,
freezing, and invalidating cache contents. It also includes bits for defining the default cache mode
and write-protect fields. The CACR is described in
(CACR).”
Freescale Semiconductor
then
else
move.l Ay, USP; move to USP
move.l USP, Ax; move from USP
OTHER_A7 = User Stack Pointer
OTHER_A7 = Supervisor Stack Pointer
Supervisor/User Stack Pointers (A7 and OTHER_A7)
Vector Base Register (VBR)
Cache Control Register (CACR)
A7 = Supervisor Stack Pointer
A7 = User Stack Pointer
MCF5235 Reference Manual, Rev. 2
Section 5.2.1.1, “Cache Control Register
Processor Register Description
—
the supervisor
3-7