MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 74

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Signal Descriptions
2-16
Test Reset
Test Clock
Test Mode Select
Test Data Input
Test Data Output
Development Serial
Clock
Breakpoint
Development Serial
Input
Development Serial
Output
Debug Data
Processor Status
Outputs
Processor Status Clock PSTCLK
Signal Name
TRST
TCLK
TMS
TDI
TDO
DSCLK
BKPT
DSI
DSO
DDATA[3:0]
PST[3:0]
Abbreviation
PST[3:0]
0000
0001
0010
0100
0101
1000
0011
0110
0111
Table 2-15. Debug Support Signals
Table 2-16. Processor Status
Continue execution
Begin execution of one instruction
Reserved
Entry into user mode
Begin execution of PULSE and WDDATA instructions
Begin execution of taken branch
Reserved
Begin execution of RTE instruction
Begin one-byte transfer on DDATA
MCF5235 Reference Manual, Rev. 2
This active-low signal is used to initialize the JTAG logic
asynchronously.
Used to synchronize the JTAG logic.
Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
Serial input for test instructions and data. TDI is sampled on the
rising edge of TCLK.
Serial output for test instructions and data. TDO is three-stateable
and is actively driven in the shift-IR and shift-DR controller states.
TDO changes on the falling edge of TCLK.
Clocks the serial communication port to the BDM module during
packet transfers.
Used to request a manual breakpoint.
This internally-synchronized signal provides data input for the serial
communication port to the BDM module.
This internally-registered signal provides serial output
communication for BDM module responses.
Display captured processor data and breakpoint status. The PSTCLK
signal can be used by the development system to know when to
sample DDATA[3:0].
Indicate core status, as shown in
synchronous with the processor clock; status is unrelated to the
current bus transfer. The PSTCLK signal can be used by the
development system to know when to sample PST[3:0].
PSTCLK indicates when the development system should sample
PST and DDATA values.
Processor Status
Function
Table
2-16. Debug mode timing is
Freescale Semiconductor
I/O
O
O
O
O
O
I
I
I
I
I
I
I