MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 748

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Index-8
eTPU
FlexCAN
GPIO
I
interrupt controller
2
C
receive descriptor active (RDAR) 19-11
receive descriptor ring start (ERDSR) 19-27
transmit buffer descriptor ring start (ETSDR) 19-27
transmit control (TCR) 19-19
transmit descriptor active (TDAR) 19-12
channel data transfer request enable
channel data transfer request overflow status
channel data transfer request status
channel interrupt enable (ETPU_CIER) 20-30
channel interrupt overflow status
channel interrupt status (ETPU_CISR) 20-27
channel n configuration (ETPU_CnCR) 20-34
channel n host service request
channel n status control (ETPU_CnSCR) 20-36
channel pending service status
channel service status (ETPU_CSSR) 20-32
coherent dual-parameter controller
engine configuration (ETPU_ECR) 20-20
MISC compare (ETPU_MISCCMPR) 20-19
module configuration (ETPU_MCR) 20-16
time base 1 visibility (ETPU_TB1R) 20-25
time base 2 visibility (ETPU_TB2R) 20-26
time base configuration (ETPU_TBCR) 20-23
control (CANCTRLn) 21-9
error and status (ERRSTATn) 21-16
error counter (ERRCNTn) 21-14
interrupt flag (IFLAGn) 21-18
interrupt mask (IMASKn) 21-18
drive strength control (DSCR_x) 12-30
pin assignment (PARx) 12-20
port clear output data (PCLRR_x) 12-18
port data direction (PDDR_x) 12-14
port output data (PODR_x) 12-12
port pin data/set data (PPDSDR_x) 12-16
address (I2ADR) 27-8
control (I2CR) 27-10
data I/O (I2DR) 27-12
frequency divider (I2FDR) 27-9
status (I2SR) 27-11
(ETPU_CDTRER) 20-31
(ETPU_CDTROSR) 20-29
(ETPU_CDTRSR) 20-28
(ETPU_CIOSR) 20-28
(ETPU_CnHSRR 20-39
(ETPU_CPSSR) 20-31
(ETPU_CDCR) 20-18
MCF5235 Reference Manual, Rev. 2
JTAG
MDHA
power management
QSPI
reset controller
RNG
SCM
interrupt acknowledge level and priority
interrupt control (ICRnx) 13-12
interrupt force high/low (INTFRCHn,
interrupt pending high/low (IPRHn, IPRLn) 13-6
interrupt request level (IRLRn) 13-11
mask high/low (IMRHn, n) 13-7
bypass 31-6
IDCODE 31-5
instruction shift (IR) 31-5
TEST_CTRL 31-6
command (MDCMR) 28-7
control (MDCR) 28-7
data size (MDDSR) 28-11
error status (MDESR) 28-10
input FIFO (MDIF) 28-12
message data size (MDMDS) 28-12
message digest registers 0 (MDDx0) 28-12
message digest registers 1 (MDDx1) 28-13
mode (MDMR) 28-4
status (MDSR) 28-8
low-power control (LPCR) 8-3
low-power interrupt control (LPICR) 8-2
address (QAR) 25-14
command RAM (QCRn) 25-14
data (QDR) 25-14
delay (QDLYR) 25-11
interrupt (QIR) 25-12
mode (QMR) 25-9
wrap (QWR) 25-12
control (RCR) 10-2
status (RSR) 10-3
control (RNGCR) 29-1
entropy (RNGER) 29-4
output FIFO (RNGOUT) 29-4
status (RNGSR) 29-3
bus master park (MPARK) 11-11
core reset status (CRSR) 11-6
core watchdog control (CWCR) 11-7
core watchdog service (CWSR) 11-8
grouped peripheral access control (GPACR) 11-17
IPSBAR 11-3
master privilege (MPR) 11-14
peripheral access control (PACRn) 11-15
(IACKLPRn) 13-11
INTFRCLn) 13-9
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1-8
Freescale Semiconductor