MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 662

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Debug Support
32-18
28–22,
20–18,
31–30
15–14
28, 12
26, 10
27, 11
29/13
12–6
25, 9
24, 8
23, 7
22, 6
21, 5
20, 4
19, 3
18, 2
17, 1
16, 0
Bits
4–2
Name
TRC
EPC
EBL
EDx
EAx
PCI
—
DI
Trigger response control. Determines how the processor responds to a completed trigger
condition. The trigger response is always displayed on DDATA.
00 Display on DDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
Reserved
Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] enables a
breakpoint trigger. Clearing it disables all breakpoints at that level.
Setting an EDx bit enables the corresponding data breakpoint condition based on the size
and placement on the processor’s local data bus. Clearing all EDx bits disables data
breakpoints.
EDLW Data longword. Entire processor’s local data bus.
EDWL Lower data word.
EDW
U
EDLL
EDLM Lower middle data byte. High-order byte of the low-order word.
EDU
M
EDUU Upper upper data byte. High-order byte of the high-order word.
Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint
comparators. This can develop a trigger based on the occurrence of a data value other
than the DBR contents.
Enable address bits. Setting an EA bit enables the corresponding address breakpoint.
Clearing all three bits disables the breakpoint.
EAI
EAR
EAL
Enable PC breakpoint. If set, this bit enables the PC breakpoint.
Breakpoint invert. If set, this bit allows execution outside a given region as defined by PBR
and PBMR to enable a trigger. If cleared, the PC breakpoint is defined within the region
defined by PBR and PBMR.
Table 32-15. TDR Field Descriptions
Upper data word.
Lower lower data byte. Low-order byte of the low-order word.
Upper middle data byte. Low-order byte of the high-order word.
Enable address breakpoint inverted. Breakpoint is based outside the range
between ABLR and ABHR.
Enable address breakpoint range. The breakpoint is based on the inclusive range
defined by ABLR and ABHR.
Enable address breakpoint low. The breakpoint is based on the address in the
ABLR.
MCF5235 Reference Manual, Rev. 2
Description
Freescale Semiconductor