MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 277

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

13.2.1.6.1 Interrupt Sources
The following tables list the interrupt sources for each interrupt request line for INTC0 and
INTC1.
Freescale Semiconductor
Sourc
10
12
13
14
15
16
17
18
19
20
21
22
11
e
1
2
3
4
5
6
7
8
9
Bits
5–3
2–0
UART0
UART1
UART2
Modul
EPOR
TMR0
TMR1
TMR2
TMR3
QSPI
SCM
DMA
I
2
e
T
C
Name
IL
IP
DONE
DONE
DONE
DONE
EPF1
EPF2
EPF3
EPF4
EPF5
EPF6
EPF7
SWTI
Table 13-13. Interupt Source Assignment For INTC0
Flag
INT
INT
INT
INT
INT
INT
INT
INT
IIF
Table 13-12. ICRnx Field Descriptions (Continued)
Interrupt level. Indicates the interrupt level assigned to each interrupt input.
Interrupt priority. Indicates the interrupt priority for internal modules within the
interrupt-level assignment. 000 represents the lowest priority and 111 represents the
highest. For the fixed level interrupt sources, the priority is fixed at the midpoint for the
level, and the IP field will always read as 000.
Edge port flag 1
Edge port flag 2
Edge port flag 3
Edge port flag 4
Edge port flag 5
Edge port flag 6
Edge port flag 7
Software watchdog timeout
DMA Channel 0 transfer complete Write DONE = 1
DMA Channel 1 transfer complete Write DONE = 1
DMA Channel 2 transfer complete Write DONE = 1
DMA Channel 3 transfer complete Write DONE = 1
UART0 interrupt
UART1 interrupt
UART2 interrupt
I
QSPI interrupt
TMR0 interrupt
TMR1 interrupt
TMR2 interrupt
TMR3 interrupt
2
C interrupt
Source Description
MCF5235 Reference Manual, Rev. 2
Not used
Description
Write EPF1 = 1
Write EPF2 = 1
Write EPF3 = 1
Write EPF4 = 1
Write EPF5 = 1
Write EPF6 = 1
Write EPF7 = 1
Cleared when service complete.
Automatically cleared
Automatically cleared
Automatically cleared
Write IIF = 0
Write 1 to appropriate QIR bit
Write 1 to appropriate TER0 bit
Write 1 to appropriate TER1 bit
Write 1 to appropriate TER2 bit
Write 1 to appropriate TER3 bit
Flag Clearing Mechanism
Memory Map/Register Definition
13-13