MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 555

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

26.4.2.3 FIFO
The FIFO is used in the UART’s receive buffer logic. The FIFO consists of three receiver holding
registers. The receive buffer consists of the FIFO and a receiver shift register connected to the
UnRXD (see
empty receiver holding register position of the FIFO. Thus, data flowing from the receiver to the
CPU is quadruple-buffered.
In addition to the data byte, three status bits, parity error (PE), framing error (FE), and received
break (RB), are appended to each data character in the FIFO; OE (overrun error) is not appended.
By programming the ERR bit in the channel’s mode register (UMR1n), status is provided in
character or block modes.
USRn[RxRDY] is set when at least one character is available to be read by the CPU. A read of the
receive buffer produces an output of data from the top of the FIFO. After the read cycle, the data
at the top of the FIFO and its associated status bits are popped and the receiver shift register can
add new data at the bottom of the FIFO. The FIFO-full status bit (FFULL) is set if all three
positions are filled with data. Either the RxRDY or FFULL bit can be selected to cause an interrupt
and either TxRDY or RxRDY can be used to generate a DMA request.
The two error modes are selected by UMR1n[ERR] as follows:
In either mode, reading the USRn does not affect the FIFO. The FIFO is popped only when the
receive buffer is read. The USRn should be read before reading the receive buffer. If all three
receiver holding registers are full, a new character is held in the receiver shift register until space
is available. However, if a second new character is received, the contents of the the character in
the receiver shift register is lost, the FIFOs are unaffected, and USRn[OE] is set when the receiver
detects the start bit of the new overrunning character.
To support flow control, the receiver can be programmed to automatically negate and assert
UnRTS, in which case the receiver automatically negates UnRTS when a valid start bit is detected
and the FIFO is full. The receiver asserts UnRTS when a FIFO position becomes available;
therefore, overrun errors can be prevented by connecting UnRTS to the UnCTS input of the
transmitting device.
Freescale Semiconductor
• In character mode (UMR1n[ERR] = 0, status is given in the USRn for the character at the
• In block mode, the USRn shows a logical OR of all characters reaching the top of the FIFO
top of the FIFO.
since the last
of the FIFO. Block mode offers a data-reception speed advantage where the software
overhead of error-checking each character cannot be tolerated. However, errors are not
detected until the check is performed at the end of an entire message—the faulting character
is not identified.
Figure
RESET ERROR STATUS
26-18). Data is assembled in the receiver shift register and loaded into the top
MCF5235 Reference Manual, Rev. 2
command. Status is updated as characters reach the top
Functional Description
26-23