MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 653

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

32.4.3
The ABLR and ABHR, shown in
that can be used as part of the trigger. These register values are compared with the address for each
transfer on the processor’s high-speed local bus. The trigger definition register (TDR) identifies
the trigger as one of three cases:
Freescale Semiconductor
1. Identical to the value in ABLR
2. Inside the range bound by ABLR and ABHR inclusive
3. Outside that same range
Bits
4–3
2–0
Address Breakpoint Registers (ABLR, ABHR)
Name
TM
TT
Table 32-5. AATR Field Descriptions (Continued)
Transfer type. Compared with the local bus transfer type signals.
00 Normal processor access
01 Reserved
10 Emulator mode access
11 Acknowledge/CPU space access
These bits also define the TT encoding for BDM memory commands. In this case, the 01
encoding indicates an external or DMA access (for backward compatibility). These bits
affect the TM bits.
Transfer modifier. Compared with the local bus transfer modifier signals, which give
supplemental information for each transfer type.
TT = 00 (normal mode):
000 Explicit cache line push
001 User data access
010 User code access
011 Reserved
100 Reserved
101 Supervisor data access
110 Supervisor code access
111 Reserved
TT = 10 (emulator mode):
0xx–100 Reserved
101 Emulator mode data access
110 Emulator mode code access
111 Reserved
TT = 11 (acknowledge/CPU space transfers):
000 CPU space access
001–111 Interrupt acknowledge levels 1–7
These bits also define the TM encoding for BDM memory commands (for backward
compatibility).
Figure
MCF5235 Reference Manual, Rev. 2
32-5, define regions in the processor’s data address space
Description
Memory Map/Register Definition
32-9