MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 436

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Enhanced Time Processing Unit (eTPU)
20-22
18–16
15–14
Bits
FPSCK
Name
CDFC
Table 20-6. ETPU_ECR Field Descriptions (Continued)
Filter prescaler clock control. Controls the prescaling of the clocks used in digital filters for
the channel input signals and TCRCLK input. The following table illustrates filter prescaler
clock control.
Filtering can be controlled independently by the engine, but all input digital filters in the
engine have the same clock prescaling. For more details, refer to the eTPU User’s Manual.
Channel digital filter control. Select a digital filtering mode for the channels when
configured as inputs for improved noise immunity. Channel digital filter control is illustrated
in the following table.
The eTPU has three digital filtering modes for the channels which provide programmable
trade-off between signal latency and noise immunity. For more information on filtering,
refer to the eTPU User’s Manual. Changing CDFC during eTPU normal input channel
operation is not recommended since it changes the behavior of the transition detection
logic while executing its operation.
CDFC
00
01
10
11
FPSC
TPU2/3 two sample mode: Using the filter clock which is the internal bus
clock divided by (2, 4, 8,..., 256) as a sampling clock (selected by
ETPU_ECR[FPSCK]), comparing two consecutive samples which agree
with each other sets the input signal state. This is the default reset state.
Reserved.
eTPU three sample mode: Similar to the TPU2/3 two sample mode, but
comparing three consecutive samples which agree with each other sets
the input signal state.
eTPU continuous mode: Signal needs to be stable for the whole filter
clock period. This mode compares all the values at the rate of system
clock divided by two, between two consecutive filter clock pulses. If all
the values agree with each other, input signal state is updated.
000
001
010
011
K
MCF5235 Reference Manual, Rev. 2
Sample on Internal
Bus Clock Divided
by:
16
2
4
8
Selected Digital Filter
Description
FPSC
100
101
110
111
K
Sample on Internal
Bus Clock Divided
128
256
by:
32
64
Freescale Semiconductor